K7I163682B_06 SAMSUNG [Samsung semiconductor], K7I163682B_06 Datasheet
K7I163682B_06
Related parts for K7I163682B_06
K7I163682B_06 Summary of contents
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... Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. * Samsung Electronics reserves the right to change products or specification without notice. 512Kx36 & 1Mx18 DDRII CIO b2 SRAM (RoHS compliant ...
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... The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques- tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. 512Kx36 & 1Mx18 DDRII CIO b2 SRAM From To ...
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... K K CLK GEN C C Notes: 1. Numbers are for x18 device. DDRII SRAM and Double Data Rate comprise a new family of products developed by Cypress, Hitachi, IDT, Micron, NEC and Samsung technology. 512Kx36 & 1Mx18 DDRII CIO b2 SRAM Organization X36 X18 * -E(F)C(I) E(F) [Package type] : E-Pb Free, F-Pb ...
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... SS TMS TDI TCK TDO 2A,3A,10A,1B,9B,10B,1C,2C,9C,1D,9D,10D,1E,2E,9E, NC 1F,9F,10F,1G,9G,10G,1J,2J,9J,1K,2K,9K 1L,9L,10L,1M,2M,9M,1N,9N,10N,1P,2P,9P Notes cannot be set to V REF 2. When ZQ pin is directly connected Not connected to chip pad internally. 512Kx36 & 1Mx18 DDRII CIO b2 SRAM K7I163682B(512Kx36 R ...
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... NC 1J,2J,3J,9J,11J,1K,2K,9K,10K,1L,3L,9L,10L 1M,2M,3M,9M,11M,1N,2N,9N,10N,11N,1P,2P,9P,10P Notes cannot be set to V REF 2. When ZQ pin is directly connected Not connected to chip pad internally. 512Kx36 & 1Mx18 DDRII CIO b2 SRAM R ...
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... K clock rising edge. Then output drivers disabled automatically to high impedance state. Echo clock operation To assure the output traceability, the SRAM provides the output Echo clock, pair of compliment clock CQ and CQ, which are synchronized with internal data output. Echo clocks run free during normal operation. ...
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... System flight time and clock skew could not be compensated in this mode. Depth Expansion Each port can be selected and deselected independently with R/W be shared among all SRAMs and provide a new LD signal for each bank. Before chip deselected, all read and write pending operations are completed. ...
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... LD=Low, "LOAD" refers to read new address inactive status with LD=High. 3. "READ" refers to read active read status with R/W=High, "WRITE" refers to write active status with R/W=Low 512Kx36 & 1Mx18 DDRII CIO b2 SRAM Case 1 SA ...
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... H ↑ H ↑ H Notes means "Don′t Care". 2. All inputs in this table must meet setup and hold time around the rising edge of input clock ↑ Assumes a WRITE cycle was initiated. 512Kx36 & 1Mx18 DDRII CIO b2 SRAM Q(A0) X Previous state X High C(t+1) ...
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... These are DC test criteria. DC design criteria is V timing parameters. - (Min)AC=-1.5V(pulse width ≤ 3ns (Min)DC= 0.3V 10. V (Max)DC= +0.3, V (Max)AC= DDQ IH IH 512Kx36 & 1Mx18 DDRII CIO b2 SRAM SYMBOL SS Commercial Industrial =1.8V ±0.1V TEST CONDITIONS V =Max ; DDQ ...
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... AC TEST CONDITIONS Parameter Core Power Supply Voltage Output Power Supply Voltage Input High/Low Level Input Reference Level Input Rise/Fall Time Output Timing Reference Level Note: Parameters are tested with RQ=250Ω 512Kx36 & 1Mx18 DDRII CIO b2 SRAM =1.8V ±0.1V SYMBOL V (AC ...
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... The specs as shown do not imply bus contention because tCHQX (0°C, 1.9V) than tCHQZ, which is a MAX parameter(worst case at 70°C, 1.7V not possible for two SRAMs on the same board such different voltage and temperature. 5. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. ...
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... Data In Data Out Address MEMORY CONTROLLER Return CLK Vt Source CLK Return CLK Vt Source CLK R=50Ω Vt=V SRAM1 Input CQ SRAM1 Input CQ SRAM4 Input CQ SRAM4 Input CQ 512Kx36 & 1Mx18 DDRII CIO b2 SRAM SYMBOL TESTCONDITION =0V OUT OUT C - CLK =1.5V. DDQ SYMBOL θ ...
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... Outputs are disabled(High-Z) one clock cycle after a NOP. 3. The second NOP cycle is not necessary for correct device operation; however, at high clock frequencies, it may be required to prevent bus contention. 512Kx36 & 1Mx18 DDRII CIO b2 SRAM NOP NOP WRITE READ ...
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... This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Reg- ister, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up, therefore, TRST signal is not required ...
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... Note pins are read as "X" ( i.e. don t care.) 512Kx36 & 1Mx18 DDRII CIO b2 SRAM Bypass Register ID Register 1 bit 32 bits 1 bit 32 bits Part Configuration Samsung JEDEC Code (28:12) 00def0wx0t0q0b0s0 00001001110 00def0wx0t0q0b0s0 00001001110 ORDER PIN ID ...
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... Output High Voltage(I =-2mA) OH Output Low Voltage(I =2mA) OL Note: 1. The input level of SRAM pin is to follow the SRAM DC specification JTAG AC TEST CONDITIONS Parameter Input High/Low Level Input Rise/Fall Time Input and Output Timing Reference Level Note: 1. See SRAM AC test output load on page 11. ...
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... K7I163682B K7I161882B 165 FBGA PACKAGE DIMENSIONS 13mm x 15mm Body, 1.0mm Bump Pitch, 11x15 Ball Array Symbol Value Units 13 ± 0 ± 0.1 B 1.3 ± 0.1 C 0.35 ± 0.05 D 512Kx36 & 1Mx18 DDRII CIO b2 SRAM Note Symbol Top View ...