K7R163684B_06 SAMSUNG [Samsung semiconductor], K7R163684B_06 Datasheet - Page 8

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K7R163684B_06

Manufacturer Part Number
K7R163684B_06
Description
512Kx36 & 1Mx18 QDRTM II b4 SRAM
Manufacturer
SAMSUNG [Samsung semiconductor]
Datasheet
K7R163684B
K7R161884B
Notes: 1. Internal burst counter is fixed as 2-bit linear, i.e. when first address is A0+0, next internal burst address is A0+1.
READ
D count=2
3. Read and write state machine can be active simultaneously.
4. State machine control timing sequence is controlled by K.
2. “READ” refers to read active status with R=Low, “READ” refers to read inactive status with R=high. “WRITE” and "WRITE" are the same case.
READ
D count=1
ALWAYS
D count=D count+1
READ ADDRESS
READ ADDRESS
INCREMENT
LOAD NEW
READ NOP
DDR READ
D count=0
READ
READ
D count=2
ALWAYS
STATE DIAGRAM
READ
POWER-UP
512Kx36 & 1Mx18 QDR
- 8 -
WRITE
WRITE
D count=2
ALWAYS
WRITE
D count=D count+1
WRITE ADDRESS
WRITE ADDRESS
INCREMENT
WRITE NOP
DDR WRITE
LOAD NEW
D count=0
WRITE
D count=1
ALWAYS
Rev. 5.0 July 2006
TM
II b4 SRAM
WRITE
D count=2

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