K7N161801A-QFCI25/20/16 SAMSUNG [Samsung semiconductor], K7N161801A-QFCI25/20/16 Datasheet - Page 17

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K7N161801A-QFCI25/20/16

Manufacturer Part Number
K7N161801A-QFCI25/20/16
Description
512Kx36 & 1Mx18 Pipelined NtRAM
Manufacturer
SAMSUNG [Samsung semiconductor]
Datasheet
K7N163601A
K7N161801A
JTAG DC OPERATING CONDITIONS
NOTE : The input level of SRAM pin is to follow the SRAM DC specification
JTAG AC TEST CONDITIONS
JTAG AC Characteristics
JTAG TIMING DIAGRAM
Power Supply Voltage
Input High Level ( 3.3V I/O / 2.5V I/O )
Input Low Level ( 3.3V I/O / 2.5V I/O )
Output High Voltage( 3.3V I/O / 2.5V I/O )
Output Low Voltage( 3.3V I/O / 2.5V I/O )
Input High/Low Level( 3.3V I/O , 2.5V I/O )
Input Rise/Fall Time( 3.3V I/O , 2.5V I/O )
Input and Output Timing Reference Level
TCK Cycle Time
TCK High Pulse Width
TCK Low Pulse Width
TMS Input Setup Time
TMS Input Hold Time
TDI Input Setup Time
TDI Input Hold Time
SRAM Input Setup Time
SRAM Input Hold Time
Clock Low to Output Valid
(SRAM)
TMS
PI
TDO
TCK
TDI
1.
In Case of I/O Pins, the Max. V
Parameter
Parameter
Parameter
IH
=V
t
DDQ
C H C H
+0.3V.
t
CLQV
Symbol
Symbol
V
TR/TF
V
V
V
V
V
IH
DD
O H
OL
I H
IL
/V
t
t
t
Symbol
MVCH
DVCH
SVCH
IL
t
t
t
t
t
t
t
t
t
t
CHCH
MVCH
CHMX
CHCL
CLCH
DVCH
CHDX
SVCH
CHSX
CLQV
512Kx36 & 1Mx18 Pipelined NtRAM
- 17 -
.
2.0 / 1.7
2.4 / 2.0
3.135
Min
-0.3
-
t
t
t
CHMX
C H D X
CHSX
1.0/1.0 , 1.0/1.0
Min
50
20
20
5
5
5
5
5
5
0
t
3.0/0 , 2.5/0
C H C L
V
Typ
Min
DDQ
3.3
-
-
-
-
/2
Max
10
V
-
-
-
-
-
-
-
-
-
0.8 / 0.7
0.4 / 0.4
3.465
DD
Max
-
+0.3
t
C L C H
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
Unit
ns
V
V
V
V
V
V
V
Nov. 2003
Note
Note
Note
Rev 3.0
1
TM

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