K7N161801A-Q(F)C(I)16 Samsung semiconductor, K7N161801A-Q(F)C(I)16 Datasheet
K7N161801A-Q(F)C(I)16
Related parts for K7N161801A-Q(F)C(I)16
K7N161801A-Q(F)C(I)16 Summary of contents
Page 1
... K7N163601A K7N161801A Document Title 512Kx36 & 1Mx18-Bit Pipelined NtRAM Revision History Rev. No. History 0.0 1. Initial document. 0.1 1. Add JTAG Scan Order 0.2 1. Add x32 org and industrial temperature . 2. Add 165FBGA package 0.3 1. Speed bin merge. From K7N1636(32/18)09A to K7N1636(32/18)01A parameter change. tOH(min)/tLZC(min) from 0.8 to 1.5 at -25 tOH(min)/tLZC(min) from 1 ...
Page 2
... K7N163601A K7N161801A 16Mb NtRAM(Flow Through / Pipelined) Ordering Informa Org. Part Number K7M161825A-QC(I)65/75 1Mx18 K7N161801A-Q(F)C(I)25/20/16/13 K7N161845A-Q(F)C(I)25/20/16/13 K7M163625A-QC(I)65/75 512Kx36 K7N163601A-Q(F)C(I)25/20/16/13 K7N163645A-Q(F)C(I)25/20/16/13 512Kx36 & 1Mx18 Pipelined NtRAM tion Speed Mode VDD FT ; Access Time(ns) Pipelined ; Cycle Time(MHz) FlowThrough 3.3 6.5/7.5 ns Pipelined 3.3 250/200/167/133MHz Pipelined 2.5 250/200/167/133MHz FlowThrough 3.3 6.5/7.5 ns Pipelined 3.3 250/200/167/133MHz Pipelined 2 ...
Page 3
... For read cycles, pipelined SRAM output data is temporarily stored by an edge triggered output register and then released to the output buffers at the next rising edge of clock. The K7N163601A and K7N161801A are implemented with -20 -16 -13 ...
Page 4
... K7N163601A K7N161801A PIN CONFIGURATION (TOP VIEW) NC/DQPc 1 DQc 0 2 DQc DDQ 4 V SSQ 5 DQc 2 6 DQc 3 7 DQc 4 8 DQc SSQ 10 V DDQ 11 DQc 6 12 DQc DQd 0 18 DQd DDQ 20 V SSQ ...
Page 5
... Burst Mode Control and A are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. OTE 0 1 512Kx36 & 1Mx18 Pipelined NtRAM 100 Pin TQFP (20mm x 14mm) K7N161801A(1Mx18) TQFP PIN NO. SYMBOL 32,33,34,35,36,37,44 V Power Supply(+3.3V) DD 45,46,47,48,49,50,80 V Ground SS ...
Page 6
... K7N163601A K7N161801A 165-PIN FBGA PACKAGE CONFIGURATIONS K7N163601A(512Kx36 CS2 C DQPc NC V DDQ D DQc DQc V DDQ E DQc DQc V DDQ F DQc DQc V DDQ G DQc DQc V DDQ DQd DQd V DDQ K DQd DQd V DDQ L DQd DQd V DDQ M DQd ...
Page 7
... K7N163601A K7N161801A 165-PIN FBGA PACKAGE CONFIGURATIONS K7N161801A(1Mx18 CS2 DDQ D NC DQb V DDQ E NC DQb V DDQ F NC DQb V DDQ G NC DQb V DDQ DQb NC V DDQ K DQb NC V DDQ L DQb NC V DDQ M DQb ...
Page 8
... K7N163601A K7N161801A FUNCTION DESCRIPTION The K7N163601A and K7N161801A are NtRAM there is transition from Read to Write, or vice versa. All inputs (with the exception LBO and ZZ) are synchronized to rising clock edges. All read, write and deselect cycles are initiated by the ADV input. Subsequent burst addresses can be internally generated by the burst advance pin (ADV) ...
Page 9
... K7N163601A K7N161801A BEGIN READ READ BURST COMMAND DS READ WRITE BURST Notes : 1. An IGNORE CLOCK EDGE cycle is not shown is the above diagram. This is because CKE HIGH only blocks the clock(CLK) input and does not change the state of the device. 2. States change on the rising edge of the clock(CLK) 512Kx36 & ...
Page 10
... K7N163601A K7N161801A TRUTH TABLES SYNCHRONOUS TRUTH TABLE ADV WE BWx ...
Page 11
... K7N163601A K7N161801A ASYNCHRONOUS TRUTH TABLE OPERATION ZZ Sleep Mode H L Read L Write L Deselected L ABSOLUTE MAXIMUM RATINGS* PARAMETER Voltage on V Supply Relative Voltage on Any Other Pin Relative to V Power Dissipation Storage Temperature Operating Temperature Storage Temperature Range Under Bias *Notes : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied ...
Page 12
... K7N163601A K7N161801A DC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL Input Leakage Current(except ZZ) Output Leakage Current Operating Current Standby Current Output Low Voltage(3.3V I/O) Output High Voltage(3.3V I/O) Output Low Voltage(2.5V I/O) Output High Voltage(2.5V I/O) Input Low Voltage(3.3V I/O) Input High Voltage(3.3V I/O) Input Low Voltage(2.5V I/O) Input High Voltage(2.5V I/O) Notes : 1. The above parameters are also guaranteed at industrial temperature range. ...
Page 13
... K7N163601A K7N161801A Output Load(A) Dout Zo=50 AC TIMING CHARACTERISTICS PARAMETER Cycle Time Clock Access Time Output Enable to Data Valid Clock High to Output Low-Z Output Hold from Clock High Output Enable Low to Output Low-Z Output Enable High to Output High-Z Clock High to Output High-Z Clock High Pulse Width ...
Page 14
... K7N163601A K7N161801A SLEEP MODE SLEEP MODE is a low current, power-down mode in which the device is deselected and current is reduced to I SLEEP MODE is dictated by the length of time the High state. After entering SLEEP MODE, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter SLEEP MODE ...
Page 15
... K7N163601A K7N161801A IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG This part contains an IEEE standard 1149.1 Compatible Test Access Port(TAP). The package pads are monitored by the Serial Scan circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not driven out of the SRAM under JTAG control ...
Page 16
... K7N163601A K7N161801A SCAN REGISTER DEFINITION Part Instruction Register 512Kx36 3 bits 1Mx18 3 bits ID REGISTER DEFINITION Revision Number Part (31:28) 512Kx36 0000 1Mx18 0000 165FBGA BOUNDARY SCAN EXIT ORDER(x36 LBO 11P 10P A 9 10R ...
Page 17
... K7N163601A K7N161801A JTAG DC OPERATING CONDITIONS Parameter Power Supply Voltage Input High Level ( 3.3V I/O / 2.5V I/O ) Input Low Level ( 3.3V I/O / 2.5V I/O ) Output High Voltage( 3.3V I/O / 2.5V I/O ) Output Low Voltage( 3.3V I/O / 2.5V I/O ) NOTE : The input level of SRAM pin is to follow the SRAM DC specification 1. In Case of I/O Pins, the Max JTAG AC TEST CONDITIONS Parameter Input High/Low Level( 3 ...
Page 18
... K7N163601A K7N161801A 512Kx36 & 1Mx18 Pipelined NtRAM - Nov. 2003 Rev 3.0 ...
Page 19
... K7N163601A K7N161801A 512Kx36 & 1Mx18 Pipelined NtRAM - Nov. 2003 Rev 3.0 ...
Page 20
... K7N163601A K7N161801A 512Kx36 & 1Mx18 Pipelined NtRAM - Nov. 2003 Rev 3.0 ...
Page 21
... K7N163601A K7N161801A 512Kx36 & 1Mx18 Pipelined NtRAM - Nov. 2003 Rev 3.0 ...
Page 22
... K7N163601A K7N161801A 512Kx36 & 1Mx18 Pipelined NtRAM - Nov. 2003 Rev 3.0 ...
Page 23
... K7N163601A K7N161801A PACKAGE DIMENSIONS 100-TQFP-1420A #1 0.65 512Kx36 & 1Mx18 Pipelined NtRAM 22.00 0.30 20.00 0.20 0.30 (0.58) 0.10 0.10 MAX 1.40 0.05 MIN 0.50 0. Units ; millimeters/Inches 0~8 + 0.10 0.127 - 0.05 16.00 0.30 0.10 MAX 14.00 0.20 (0.83) 0.50 0.10 1.60 MAX 0.10 TM Nov. 2003 Rev 3.0 ...
Page 24
... K7N163601A K7N161801A 165 FBGA PACKAGE DIMENSIONS 13mm x 15mm Body, 1.0mm Bump Pitch, 11x15 Ball Array C E Symbol Value Units 0.1 C 1.3 0.1 D 0.35 0.05 512Kx36 & 1Mx18 Pipelined NtRAM Note Symbol Top View Side View D Bottom View ...