K7N161801A-Q(F)C(I)16 Samsung semiconductor, K7N161801A-Q(F)C(I)16 Datasheet - Page 13

• Manufacturer Part Number: K7N161801A-Q(F)C(I)16
• Description: 512Kx36 & 1Mx18 Pipelined NtRAM
• Manufacturer: Samsung semiconductor

Dout
K7N163601A
K7N161801A
AC TIMING CHARACTERISTICS
Note s : 1. The above parameters are also guaranteed at industrial temperature range.
Cycle Time
Clock Access Time
Output Enable to Data Valid
Clock High to Output Low-Z
Output Hold from Clock High
Output Enable Low to Output Low-Z
Output Enable High to Output High-Z
Clock High to Output High-Z
Clock High Pulse Width
Clock Low Pulse Width
Address Setup to Clock High
CKE Setup to Clock High
Data Setup to Clock High
Write Setup to Clock High (WE, BW
Address Advance Setup to Clock High
Chip Select Setup to Clock High
Address Hold from Clock High
CKE Hold from Clock High
Data Hold from Clock High
Write Hold from Clock High (WE , BW
Address Advance Hold from Clock High
Chip Select Hold from Clock High
ZZ High to Power Down
ZZ Low to Power Up
2 . All address inputs must meet the specified setup and hold times for all rising clock(CLK) edges when ADV is sampled low and CS is sampled
3. Chip selects must be valid at each rising edge of CLK(when ADV is Low) to remain enabled.
4. A write cycle is defined by WE low having been registered into the device at ADV Low, A Read cycle is defined by WE High with ADV Low,
5. To avoid bus contention, At a given voltage and temperature t
It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
(0 C,3.465V) than t
Both cases must meet setup and hold times.
The specs as shown do not imply bus contention because t
Output Load(A)
PARAMETER
Zo=50
H Z C
, which is a Max. parameter(worst case at 70 C,3.135V)
X
)
X
)
RL=50
SYMBOL
30pF*
t
t
t
* Including Scope and Jig Capacitance
t
(V
t
HZOE
t
t
ADVS
t
t
ADVH
t
t
t
t
LZOE
t
t
t
CYC
t
t
HZC
t
t
t
CES
t
CSS
t
CEH
t
CSH
PDS
PUS
LZC
OH
WS
WH
CD
OE
CH
CL
AS
DS
AH
DH
DD
=3.3V+0.165V/-0.165V, T
VL=1.5V for 3.3V I/O
MIN
4.0
1.5
1.5
1.7
1.7
1.2
1.2
1.2
1.2
1.2
1.2
0.3
0.3
0.3
0.3
0.3
0.3
0
2
2
V
-
-
-
-
DDQ
-25
512Kx36 & 1Mx18 Pipelined NtRAM
Fig. 1
LZC
LZC
- 13 -
/2 for 2.5V I/O
MAX
2.6
2.6
2.6
2.6
is more than t
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
is a Min. parameter that is worst case at totally different test conditions
MIN
5.0
1.5
1.5
2.0
2.0
1.4
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
0.4
0
2
2
-
-
-
-
-20
HZC.
A
MAX
=0 to 70 C)
3.2
3.2
3.0
3.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
353
Output Load(B),
(for t
Dout
MIN
6.0
1.5
1.5
2.2
2.2
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
LZC
0
2
2
-
-
-
-
1538
, t
-16
LZOE
MAX
3.5
3.5
3.0
3.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
, t
HZOE
MIN
7.5
1.5
1.5
3.0
3.0
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
& t
0
2
2
-
-
-
-
HZC
-13
+3.3V for 3.3V I/O
/+2.5V for 2.5V I/O
319
5pF*
)
MAX
4.2
4.2
3.5
3.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1667
Nov. 2003
UNIT
cycle
cycle
Rev 3.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TM