K7N161801A-Q(F)C(I)16 Samsung semiconductor, K7N161801A-Q(F)C(I)16 Datasheet - Page 3

• Manufacturer Part Number: K7N161801A-Q(F)C(I)16
• Description: 512Kx36 & 1Mx18 Pipelined NtRAM
• Manufacturer: Samsung semiconductor

LOGIC BLOCK DIAGRAM
K7N163601A
K7N161801A
512Kx36 & 1Mx18-Bit Pipelined NtRAM
FEATURES
• 3.3V+0.165V/-0.165V Power Supply.
• I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O
• Byte Writable Function.
• Enable clock and suspend operation.
• Single READ/WRITE control pin.
• Self-Timed Write Cycle.
• Three Chip Enable for simple depth expansion with no da ta-
• A interleaved burst or a linear burst mode.
• Asynchronous output enable control.
• Power Down mode.
• 100-TQFP-1420A
• 165FBGA(11x15 ball aray) with body size of 13mmx15mm.
• Operating in commeical and industrial temperature range.
FAST ACCESS TIMES
(x=a,b,c,d or a,b)
A [0:18]or
A [0:19]
C L K
C K E
CS
CS
CS
ADV
W E
B W
O E
ZZ
DQa
DQPa ~ DQPd
or 2.5V+0.4V/-0.125V for 2.5V I/O.
Cycle Time
Clock Access Time
Output Enable Access Time
contention .
1
2
2
x
0
PARAMETER
~ DQd
7
or D Q a
K
0
REGISTER
ADDRESS
~ DQb
Symbol -25
tCYC
tCD
tOE
8
4.0
2.6
2.6
A
2
~A
-20
5.0
3.2
3.2
18
or A
REGISTER
ADDRESS
-16
6.0
3.5
3.5
WRITE
LBO
A
2
~A
0
~A
-13
7.5
4.2
4.2
19
1
CONTROL
LOGIC
COUNTER
Unit
ADDRESS
NtRAM
ns
ns
ns
BURST
512Kx36 & 1Mx18 Pipelined NtRAM
REGISTER
ADDRESS
- 3 -
TM
WRITE
TM
and No Turnaround Random Access Memory are trademarks of Samsung.
GENERAL DESCRIPTION
chronous Static SRAMs.
The N tRAM
lizes all the bandwidth in any combination of operating cycles.
Address, data inputs, and all control signals except output
enable and linear burst order are synchronized to input clock.
Burst order control must be tied "High or Low".
Asynchronous inputs include the sleep mode enable(ZZ).
Output Enable controls the outputs at any given time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-chip
write pulse generation
and provides increased timing flexibility for incoming signals.
For read cycles, pipelined SRAM output data is temporarily
stored by an edge triggered output register and then released
to the output buffers at the next rising edge of clock.
The K7N163601A and K7N161801A are implemented with
SAMSUNG s high performance CMOS technology and is avail-
able in 100pin TQFP and 165FBGA packages. Multiple power
and ground pins minimize ground bounce.
The K7N163601A and K7N161801A are 18,874,368-bits Syn-
A
0
~A
1
TM
, or No Turnaround Random Access Memory uti-
36 or 18
K
K
REGISTER
REGISTER
DATA-IN
DATA-IN
512Kx36, 1Mx18
MEMORY
ARRAY
K
REGISTER
OUTPUT
Nov. 2003
BUFFER
Rev 3.0
TM