K7N161801M SAMSUNG [Samsung semiconductor], K7N161801M Datasheet
K7N161801M
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K7N161801M Summary of contents
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... K7N163601M K7N161801M Document Title 512Kx36 & 1Mx18-Bit Pipelined NtRAM Revision History Rev. No. History 0.0 1. Initial document. 0.1 1. Update ICC & ISB values. 0.2 1. Change I value from 80mA to 110mA at -67 Change I value from 70mA to 90mA at - Change I value from 60mA to 80mA at - 0.3 1. Change pin allocation at 119BGA . ...
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... For read cycles, pipelined SRAM output data is temporarily stored by an edge triggered output register and then released to the output buffers at the next rising edge of clock. The K7N163601M and K7N161801M are implemented with ns SAMSUNG s high performance CMOS technology and is avail- ns able in 100pin TQFP and 119BGA packages ...
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... K7N163601M K7N161801M PIN CONFIGURATION (TOP VIEW) DQPc 1 DQc 0 2 DQc DDQ 4 V SSQ 5 DQc 2 6 DQc 3 7 DQc 4 8 DQc SSQ 10 V DDQ 11 DQc 6 12 DQc DQd 0 18 DQd DDQ 20 V SSQ ...
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... A and A are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. OTE 0 1 512Kx36 & 1Mx18 Pipelined NtRAM 100 Pin TQFP (20mm x 14mm) K7N161801M(1Mx18) TQFP PIN NO. SYMBOL PIN NAME V Power Supply(+3.3V Ground ...
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... K7N163601M K7N161801M 119BGA PACKAGE PIN CONFIGURATIONS K7N163601M(512Kx36 DDQ DQc DQPc E DQc DQc F V DQc DDQ G DQc DQc H DQc DQc DDQ DD K DQd DQd L DQd DQd M V DQd DDQ N DQd DQd P DQd DQPd ...
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... K7N163601M K7N161801M 119BGA PACKAGE PIN CONFIGURATIONS 119BGA PACKAGE PIN CONFIGURATIONS K7N161801M(1Mx18 DDQ DQb DQb DDQ G NC DQb H DQb DDQ DQb L DQb DQb DDQ N DQb DQPb ...
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... K7N163601M K7N161801M FUNCTION DESCRIPTION The K7N163601M and K7N161801M are NtRAM there is transition from Read to Write, or vice versa. All inputs (with the exception of OE, LBO and ZZ) are synchronized to rising clock edges. All read, write and deselect cycles are initiated by the ADV input. Subsequent burst addresses can be internally generated by the burst advance pin (ADV) ...
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... K7N163601M K7N161801M BEGIN READ READ BURST BURST READ COMMAND DS READ WRITE BURST Notes : 1. An IGNORE CLOCK EDGE cycle is not shown is the above diagram. This is because CKE HIGH only blocks the clock(CLK) input and does not change the state of the device. 2. States change on the rising edge of the clock(CLK) 512Kx36 & ...
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... K7N163601M K7N161801M TRUTH TABLES SYNCHRONOUS TRUTH TABLE ADV WE BWx ...
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... K7N163601M K7N161801M ASYNCHRONOUS TRUTH TABLE OPERATION ZZ OE Sleep Mode H L Read L Write L Deselected L ABSOLUTE MAXIMUM RATINGS* PARAMETER Voltage on V Supply Relative Voltage on Any Other Pin Relative Power Dissipation Storage Temperature Operating Temperature Storage Temperature Range Under Bias *Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied ...
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... K7N163601M K7N161801M DC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL Input Leakage Current(except ZZ Output Leakage Current I OL Operating Current Standby Current I SB1 I SB2 Output Low Voltage(3.3V I/ Output High Voltage(3.3V I/ Output Low Voltage(2.5V I/ Output High Voltage(2.5V I/ Input Low Voltage(3.3V I/O) ...
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... K7N163601M K7N161801M Output Load(A) Dout Zo=50 AC TIMING CHARACTERISTICS PARAMETER Cycle Time Clock Access Time Output Enable to Data Valid Clock High to Output Low-Z Output Hold from Clock High Output Enable Low to Output Low-Z Output Enable High to Output High-Z Clock High to Output High-Z Clock High Pulse Width ...
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... K7N163601M K7N161801M SLEEP MODE SLEEP MODE is a low current, power-down mode in which the device is deselected and current is reduced to I SLEEP MODE is dictated by the length of time the High state. After entering SLEEP MODE, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter SLEEP MODE ...
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... K7N163601M K7N161801M 512Kx36 & 1Mx18 Pipelined NtRAM - December 1999 Rev 1.0 ...
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... K7N163601M K7N161801M 512Kx36 & 1Mx18 Pipelined NtRAM - December 1999 Rev 1.0 ...
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... K7N163601M K7N161801M 512Kx36 & 1Mx18 Pipelined NtRAM - December 1999 Rev 1.0 ...
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... K7N163601M K7N161801M 512Kx36 & 1Mx18 Pipelined NtRAM - December 1999 Rev 1.0 ...
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... K7N163601M K7N161801M 512Kx36 & 1Mx18 Pipelined NtRAM - December 1999 Rev 1.0 ...
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... K7N163601M K7N161801M PACKAGE DIMENSIONS 100-TQFP-1420A 22.00 20.00 #1 0.65 512Kx36 & 1Mx18 Pipelined NtRAM 0.30 0.20 16.00 0.30 14.00 0.20 (0.83) (0.58) 0.30 0.10 0.10 MAX 1.40 1.60 MAX 0.10 0.05 MIN 0.50 0. Units ; millimeters/Inches 0~8 + 0.10 0.127 - 0.05 0.10 MAX 0.50 0.10 December 1999 Rev 1.0 ...
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... K7N163601M K7N161801M 119BGA PACKAGE DIMENSIONS 14.00 0.10 Indicator of Ball(1A) Location C1.00 0.60 0.10 12.50 0.10 512Kx36 & 1Mx18 Pipelined NtRAM 22.00 0.10 20.50 0.10 C0.70 1.50REF NOTE : 0.60 0.10 1. All Dimensions are in Millimeters. 2. Solder Ball to PCB Offset : 0.10 MAX. 3. PCB to Cavity Offset : 0.10 MAX 1.27 1.27 0.750 0.15 December 1999 Rev 1.0 ...