K7N161801M SAMSUNG [Samsung semiconductor], K7N161801M Datasheet - Page 7
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K7N161801M
Manufacturer Part Number
K7N161801M
Description
512Kx36 & 1Mx18-Bit Pipelined NtRAM TM
Manufacturer
SAMSUNG [Samsung semiconductor]
Datasheet
1.K7N161801M.pdf
(20 pages)
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K7N163601M
K7N161801M
FUNCTION DESCRIPTION
The K7N163601M and K7N161801M are NtRAM
there is transition from Read to Write, or vice versa.
All inputs (with the exception of OE, LBO and ZZ) are synchronized to rising clock edges.
All read, write and deselect cycles are initiated by the ADV input. Subsequent burst addresses can be internally generated by the
burst advance pin (ADV). ADV should be driven to Low once the device has been deselected in order to load a new address for next
operation.
Clock Enable(CKE) pin allows the operation of the chip to be suspended as long as necessary. When CKE is high, all synchronous
inputs are ignored and the internal device registers will hold their previous values.
NtRAM
are active .
Output Enable(OE) can be used to disable the output at any given time.
Read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the
address register, CKE is driven low, all three chip enables(CS
high, and ADV driven low.The internal array is read between the first rising edge and the second rising edge of the clock and the data
is latched in the output register. At the second clock edge the data is driven out of the SRAM. Also during read operation OE must
be driven low for the device to drive out the requested data.
Write operation occurs when WE is driven low at the rising edge of the clock. BW[d:a] can be used for byte write operation. The pipe-
lined NtRAM
At the first rising edge of the clock, WE and address are registered, and the data associated with that address is required two cycle
later.
Subsequent addresses are generated by ADV High for the burst access as shown below. The starting point of the burst seguence is
provided by the external address. The burst address counter wraps around to its initial state upon completion.
The burst sequence is determined by the state of the LBO pin. When this pin is low, linear burst sequence is selected.
And when this pin is high, Interleaved burst sequence is selected.
During normal operation, ZZ must be driven low. When ZZ is driven high, the SRAM will enter a Power Sleep Mode after 2 cycles. At
this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2 cycles of wake up
time.
BURST SEQUENCE TABLE
BQ TABLE
Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed
LBO PIN
LBO PIN
TM
latches external address and initiates a cycle, when CKE, ADV are driven to low and all three chip enables(CS
Fourth Address
Fourth Address
TM
First Address
First Address
uses a late-late write cycle to utilize 100% of the bandwidth.
HIGH
LOW
A
A
0
0
1
1
0
0
1
1
1
1
Case 1
Case 1
TM
designed to sustain 100% bus bandwidth by eliminating turnaround cycle when
A
A
0
1
0
1
0
1
0
1
0
0
512Kx36 & 1Mx18 Pipelined NtRAM
1
, CS
- 7 -
A
A
0
0
1
1
2
0
1
1
0
1
, CS
1
Case 2
Case 2
2
) are active, the write enable input signals WE are driven
.
A
A
1
0
1
0
1
0
1
0
0
0
A
A
1
1
0
0
1
1
0
0
1
1
Case 3
Case 3
A
A
0
1
0
1
0
1
0
1
0
(Interleaved Burst, LBO=High)
0
(Linear Burst, LBO=Low)
A
A
1
1
0
0
1
0
0
1
1
December 1999
1
Case 4
Case 4
1
, CS
Rev 1.0
2
A
A
1
0
1
0
1
0
1
0
, CS
0
0
TM
2
)