K7N161845M SAMSUNG [Samsung semiconductor], K7N161845M Datasheet - Page 2

• Manufacturer Part Number: K7N161845M
• Description: 512Kx36 & 1Mx18-Bit Pipelined NtRAMTM
• Manufacturer: SAMSUNG [Samsung semiconductor]

K7N163645M
K7N161845M
LOGIC BLOCK DIAGRAM
FEATURES
FAST ACCESS TIMES
512Kx36 & 1Mx18-Bit Pipelined NtRAM
• 2.5V 5% Power Supply.
• Byte Writable Function.
• Enable clock and suspend operation.
• Single READ/WRITE control pin.
• Self-Timed Write Cycle.
• Three Chip Enable for simple depth expansion with no data
• A interleaved burst or a linear burst mode.
• Asynchronous output enable control.
• Power Down mode.
• TTL-Level Three-State Outputs.
• 100-TQFP-1420A / 119BGA(7x17 Ball Grid Array Package).
(x=a,b,c,d or a,b)
A [0:18]or
A [0:19]
CLK
CKE
CS
CS
CS
ADV
WE
BW
OE
ZZ
DQa
DQPa ~ DQPd
Cycle Time
Clock Access Time
Output Enable Access Time
contention .
1
2
2
x
0
~ DQd
PARAMETER
7
or DQa
K
0
REGISTER
ADDRESS
~ DQb
Symbol -16 -15 -13 -10 Unit
8
t
t
t
CYC
CD
OE
A
6.0 6.7 7.5 10
3.5 3.8 4.2 5.0
3.5 3.8 4.2 5.0
2
~A
18
or A
REGISTER
ADDRESS
WRITE
LBO
A
2
~A
0
~A
19
1
CONTROL
LOGIC
COUNTER
ADDRESS
ns
ns
ns
NtRAM
BURST
512Kx36 & 1Mx18 Pipelined NtRAM
REGISTER
ADDRESS
- 2 -
TM
WRITE
TM
and No Turnaround Random Access Memory are trademarks of Samsung.
GENERAL DESCRIPTION
The K7N163645M and K7N161845M are 18,874,368-bits Syn-
chronous Static SRAMs.
The NtRAM
lizes all the bandwidth in any combination of operating cycles.
Address, data inputs, and all control signals except output
enable and linear burst order are synchronized to input clock.
Burst order control must be tied "High or Low".
Asynchronous inputs include the sleep mode enable(ZZ).
Output Enable controls the outputs at any given time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-chip
write pulse generation
and provides increased timing flexibility for incoming signals.
For read cycles, pipelined SRAM output data is temporarily
stored by an edge triggered output register and then released
to the output buffers at the next rising edge of clock.
The K7N163645M and K7N161845M are implemented with
SAMSUNG s high performance CMOS technology and is avail-
able in 100pin TQFP and 119BGA packages. Multiple power
and ground pins minimize ground bounce.
A
0
~A
1
TM
, or No Turnaround Random Access Memory uti-
36 or 18
K
K
REGISTER
REGISTER
DATA-IN
DATA-IN
512Kx36 , 1Mx18
MEMORY
ARRAY
K
January 2000
REGISTER
OUTPUT
BUFFER
Rev 1.0
TM