K6T4016C3B-B SAMSUNG [Samsung semiconductor], K6T4016C3B-B Datasheet
K6T4016C3B-B
Related parts for K6T4016C3B-B
K6T4016C3B-B Summary of contents
Page 1
... K6T4016C3B Family Document Title 256Kx16 bit Low Power CMOS Static RAM Revision History Revision No. History 0.0 Initial draft 0.1 Revise - Die name change ; 1.0 Finalize 2.0 Revise - Operating current update and release. I (Read/Write) = 30/ (Read/Write) = 30/60 CC1 I = 160 130mA CC2 3.0 Revise - Change datasheet format - Remove I write value from table ...
Page 2
... Organization: 256Kx16 Power Supply Voltage: 4.5~5.5V Low Data Retention Voltage: 2V(Min) Three state output and TTL Compatible Package Type: 44-TSOP2-400F/R PRODUCT FAMILY Product Family Operating Temperature Vcc Range K6T4016C3B-B Commercial(0~70 C) K6T4016C3B-F Industrial(-40~ The parameter is measured with 50pF test load. PIN DESCRIPTION A4 1 ...
Page 3
... Mode Power Deselected Standby Output Disabled Active Output Disabled Active Lower Byte Read Active Upper Byte Read Active Word Read Active Lower Byte Write Active Upper Byte Write Active Word Write Active Unit Remark K6T4016C3B-B C K6T4016C3B Revision 5.0 May 2001 ...
Page 4
... K6T4016C3B Family RECOMMENDED DC OPERATING CONDITIONS Item Supply voltage Ground Input high voltage Input low voltage Note: 1. Commercial Product otherwise specified A Industrial Product otherwise specified A 2. Overshoot: V +3.0V in case of pulse width CC 3. Undershoot: -3.0V in case of pulse width 30ns 4. Overshoot and undershoot are sampled, not 100% tested. ...
Page 5
... K6T4016C3B Family AC OPERATING CONDITIONS TEST CONDITIONS (Test Load and Test Input/Output Reference) Input pulse level: 0.8 to 2.4V Input rising and falling time: 5ns Input and output reference voltage: 1.5V Output load (See right): C =100pF+1TTL L C =50pF+1TTL L AC CHARACTERISTICS (Vcc=4.5~5.5V, Commercial product: T Parameter List Read cycle time ...
Page 6
... K6T4016C3B Family TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) Address Data Out Previous Data Valid TIMING WAVEFORM OF READ CYCLE(2) Address CS UB Data out High-Z NOTES (READ CYCLE and are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage ...
Page 7
... K6T4016C3B Family TIMING WAVEFORM OF WRITE CYCLE(1) Address CS UB Data in Data Undefined Data out TIMING WAVEFORM OF WRITE CYCLE(2) Address CS UB Data in Data out (WE Controlled CW( WP(1) t AS(3) t High-Z t WHZ (CS Controlled AS(3) CW( WP( High-Z 7 CMOS SRAM ...
Page 8
... K6T4016C3B Family TIMING WAVEFORM OF WRITE CYCLE(3) Address CS UB Data in Data out NOTES (WRITE CYCLE wri e occurs during the overlap for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transi- tion when CS goes high and WE goes high. The t 2 ...
Page 9
... K6T4016C3B Family PACKAGE DIMENSIONS 44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F) #44 #1 18.81 MAX. 0.741 18.41 0.725 0.004 0.35 0.805 0. 0.032 0.014 0.004 44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400R) #1 #44 18.81 MAX. 0.741 18.41 0.725 0.35 0.805 0. 0.032 0.014 0.004 #23 11.76 0.20 0.463 0.008 #22 1.00 0.10 0.039 0.004 1.20 MAX. 0.047 ...