U3742BM-M3FL ATMEL [ATMEL Corporation], U3742BM-M3FL Datasheet
U3742BM-M3FL
Related parts for U3742BM-M3FL
U3742BM-M3FL Summary of contents
Page 1
... Power Management (Polling) is also Possible by Means of a Separate Pin via the Microcontroller Description The U3742BM is a multi-chip PLL receiver device supplied in an SO20 package. It has been especially developed for the demands of RF low-cost data transmission systems with data rates from 1 kBaud to 10 kBaud (1 kBaud to 3.2 kBaud for FSK) in Manches- ter or Bi-phase code ...
Page 2
... Encoder ATARx9x Keys XTO Figure 2. Block Diagram FSK/ASK CDEM RSSI SENS AVCC AGND DGND MIXVCC LNAGND LNA_IN U3742BM 2 U3742BM PLL Antenna Antenna VCO Power LNA amp. FSK/ASK- Dem_out Demodulator and data filter RSSI Limiter out Sensitivity Polling circuit IF Amp reduction control logic 4 ...
Page 3
... LFGND Ground VCO 14 XTO Crystal oscillator 15 DVCC Digital power supply 4735A–RKE–11/03 20 DATA 1 SENS 19 FSK/ASK 2 ENABLE 18 3 TEST CDEM 17 4 RSSI AVCC MODE 5 16 AGND DVCC DGND 15 6 MIXVCC 7 14 XTO 8 13 LFGND LNAGND 9 12 LNA_IN LFVCC U3742BM 3 ...
Page 4
... XTO must be considered. Figure 4. PLL Peripherals U3742BM 4 is divided by a factor of 64. The divided frequency is compared LO by the phase frequency detector. The current output of the phase frequency XTO for the VCO ...
Page 5
... LNA_IN. The input impedance of that pin is provided in the electrical parame- ters. The parasitic board inductances and capacitances also influence the input matching. The RF receiver U3742BM exhibits its highest sensitivity at the best signal-to- noise ratio in the LNA. Hence, noise matching is the best choice for designing the trans- formation network ...
Page 6
... LNAGND U3742BM 9 L LNA_IN 25n 22p 100p L 3 TOKO LL2012 47n F47NJ L 2 TOKO LL2012 F82NJ 5 1 B3551 IN OUT 82n 6 2 IN_GND OUT_GND CASE_GND LNAGND U3742BM 9 LNA_IN 25n 100p 39n TOKO LL2012 F39NJ 4735A–RKE–11/03 ...
Page 7
... The IF center frequency determine the center frequency. The receiver U3742BM - M3 employs an IF bandwidth of B together with the U2741B in FSK and ASK mode. RSSI Amplifier The subsequent RSSI amplifier enhances the output signal of the IF amplifier before it is fed into the demodulator. The dynamic range of this amplifier is DR RSSI amplifier is operated within its linear range, the best S/N ratio is maintained in ASK mode ...
Page 8
... If the receiver is already active, the data stream at pin DATA will disappear when the input signal is lower than defined by the reduced sensitivity. Instead of the data stream, the pattern according to Figure 9 on page 9 is issued at pin DATA to indi- cate that the receiver is still active. U3742BM Ig(V ) LNA_IN 50k I U3742BM 1.6 1.5 1.4 1.3 1.2 1.1 1.0 -40°C 0.9 25°C ...
Page 9
... Receiver” on page 19). BR_Range must be set in accordance to the used baud rate. The U3742BM is designed to operate with data coding where the DC level of the data signal is 50%. This is valid for Manchester and Bi-phase coding. If other modulation schemes are used, the DC level should always remain within the range of V ...
Page 10
... Receiving The RF receiver U3742BM can be operated with and without a SAW front-end filter typical automotive application, a SAW filter is used to achieve better selectivity. The Characteristics selectivity with and without a SAW front-end filter is illustrated in Figure 10. This exam- ple relates to ASK mode. FSK mode exhibits similar behavior. Note that the mirror frequency is reduced ...
Page 11
... H: Europe(:14) f DVCC XTO 15 XTO 14 = 2.0383 µs) Clk = 2.0697 µs) Clk and on the logical state of pin MODE. XTO ). Clk = 8 ´ T XClk Clk = 4 ´ T XClk Clk = 2 ´ T XClk Clk = 1 ´ T XClk Clk U3742BM . T controls Clk Clk = 315 MHz is Send is defined XClk 11 ...
Page 12
... Polling Mode Sleep Mode U3742BM 12 According to Figure 13 on page 14, the receiver stays in polling mode in a continuous cycle of three different modes. In sleep mode, the signal processing circuitry is disabled for the time period T while consuming low current of I Sleep period all signal processing circuits are enabled and settled. In the following bit ...
Page 13
... the check will be continued the bit check will be terminated and the receiver 1/f Sig Lim_min T Lim_max . The time resolution when defining T XClk ( DATA_L_min DATA_H_min U3742BM and Lim_min is smaller than ee and Lim_min and Lim_min ) is defined 13 ...
Page 14
... The receiver is turned on permanently and passes the data stream to the connected microcontroller. It can be set to Sleep mode through an OFF command via pin DATA or ENABLE Son OFF command U3742BM 14 Sleep: 5-bit word defined by Sleep0 to Sleep4 in OPMODE register X : Extension factor defined by Sleep XSleep ...
Page 15
... Bit check failed (CV_Lim < Lim_min) 1/2 Bit 1112 Bit check mode U3742BM 1/2 Bit 1/2 Bit Receiving mode Bit check ok 1/2 Bit 151617 1011121314 Sleep mode Bit check ok 1/2 Bit ...
Page 16
... Figure 17. Timing Diagram for Failed Bit Check (Condition: CV_Lim ³ Lim_max) (Lim_min = 14, Lim_max = 24) Enable IC Bit check Dem_out 0 Bit check counter Startup mode Duration of the Bit Check Receiving Mode Digital Signal Processing U3742BM 16 1/2 Bit 10 1112 ...
Page 17
... Figure 20 gives an example where Dem_out remains Low after the receiver is in receiving mode tmin1 CV_Lim < Lim_min or CV_Lim t ee Bit check mode Receiving mode U3742BM is to some extent affected by the pre- DATA_min ee DATA_min DATA_L_max tmin2 Lim_max t tmin2 DATA_L_max ...
Page 18
... Switching the Receiver Back to Sleep Mode Figure 21. Timing Diagram of the OFF-command via Pin DATA t 1 Out1 (microcontroller) DATA (U3742BM) X Serial bi-directional X data line Receiving mode U3742BM 18 After the end of data transmission, the receiver remains active and random noise pulses appear at pin DATA. The edge-to-edge time period t pulses is equal to or slightly higher than T The receiver can be set back to polling mode via pin DATA or via pin ENABLE ...
Page 19
... Doze t off The U3742BM receiver is configured via two 12-bit RAM registers called OPMODE and LIMIT. The registers can be programmed by means of the bi-directional DATA port. If the register contents have changed due to a voltage drop, this condition is indicated by a certain output pattern called reset marker (RM). The receiver must be reprogrammed in that case ...
Page 20
... Baud0 Table 5. Effect of the Configuration Word N N Bitcheck BitChk1 Table 6. Effect of the Configuration Bit Reserved Reserved Bit 0 1 U3742BM 20 Bit 6 Bit 7 Bit 8 Bit Bitcheck POUT BitChk0 POUT Sleep4 Sleep3 Lim_min Baud Rate Range/Extension Factor for Bit Check Limits (XLim) BR_Range0 (application USA/Europe: BR_Range0 = 1 ...
Page 21
... U3742BM Start Value for Sleep Counter = Sleep × Xsleep × 1024 × Sleep » 2ms for XSleep = 1 in US/European applications 22.96 ms, Europe 23.31 ms) (Default) Sleep Sleep . . . (Permanent sleep mode) = Sleep × Xsleep × 1024 × T ...
Page 22
... The U3742BM has an integrated power-on reset (POR) and brown-out detection cir- cuitry to provide a mechanism to preserve the RAM register information. According to Figure 23, a power-on reset is generated if the supply voltage V below the threshold voltage V ThReset configuration registers in that condition. Once V ...
Page 23
... Figure 24. Timing of the Register Programming t 1 Out1 (microcontroller) DATA (U3742BM) X Serial bi-directional X data line Receiving mode Programming the Configuration Register 4735A–RKE–11/ Bit 1 Bit 2 ("0") ("1") (Startbit) (Register- select) Programming frame The configuration registers are programmed serially via the bi-directional data line according to Figure 24 and Figure 25 ...
Page 24
... Junction temperature Storage temperature Ambient temperature Maximum input level, input matched Thermal Resistance Parameters Junction ambient U3742BM 24 During programming, the LNA, LO, low-pass filter, IF-amplifier and the FSK/ASK Manchester demodulator are disabled. The programming start pulse t initiates the programming of the configuration registers bit 1 is set to '1', it represents the OFF-command to set the receiver back to polling mode at the same time ...
Page 25
... BR_Range1 ´ 2 µs/T 1.8 3.2 BR_Range2 ´ 2 µs/T 3.2 5.6 BR_Range3 ´ 2 µs/T 5.6 10.0 9 ´ T 147 11 ´ T 179 9 ´ ´ ´ T 36.7 11 ´ T 44.8 9 ´ T 18.3 11 ´ T 22.4 U3742BM Typ. Max. Unit /10) µs XTO /14) µs XTO ´ T µs Clk ´ T µs Clk ´ T µs Clk ´ T µs Clk ´ ...
Page 26
... Figure 24) Programming window (Figure 21, Figure 24) Time frame of a bit (Figure 24) Programming pulse (Figure 21, Figure 24) U3742BM 26 = -40 ° +105 ° 4 5 6.76438 Mhz Oscillator 4.90625 Mhz Oscillator (Mode 1) Min. Typ. Max. Min. 2169 1085 542 ...
Page 27
... RF in Input matched according to Figure 6, BER £ ASK mode f = 432.92 MHz osc at 1 MHz at 10 MHz at ±f XTO U3742BM = 433.92 MHz and f = 315 MHz, unless other (Mode 0) Variable Oscillator Typ. Max. Min. Typ. 128 ´ T 261 Clk 258 ´ T ...
Page 28
... V amb S Sensitivity variation ASK for full operating range including IF filter = 25 ° compared amb S Input sensitivity FSK Input sensitivity FSK U3742BM 28 = -40°C to +105° Test Conditions For best LO noise (design parameter) = 820 4.7 nF ...
Page 29
... SNR 10 ASK SNR 2 FSK RSSI f 0.11 0.16 cu_DF 39 CDEM 22 12 8.2 27 CDEM 15 t ee_sig 2.5 3 4.3 5.4 7.6 9.5 13.6 17.0 t ee_sig , S P Ref_Red U3742BM Max. Unit -1.5 dB -1 kHz 50 kHz 0.20 kHz 1000 µs 560 µs 320 µs 180 µs 3.7 kHz 6.5 kHz 11.4 kHz 20.4 ...
Page 30
... Low-level input voltage - High-level input voltage ENABLE input - Low-level input voltage - High-level input voltage MODE input - Low-level input voltage - High-level input voltage TEST input - Low-level input voltage U3742BM 30 = -40°C to +105° Test Conditions = 25 ° amb ...
Page 31
... Ordering Information Extended Type Number U3742BM-M3FL U3742BM-M3FLG3 Package Information Package SO20 Dimensions in mm 0.4 1. 4735A–RKE–11/03 Package SO20 SO20 12.95 12.70 2.35 0.25 0.10 11. U3742BM Remarks Tube Taped and reeled 9.15 8.65 7.5 7.3 0.25 10.50 10.20 technical drawings according to DIN specifications 31 ...
Page 32
Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 ...