T5761 ATMEL [ATMEL Corporation], T5761 Datasheet
T5761
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T5761 Summary of contents
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... UHF ASK/FSK Receiver Description The T5760/T5761 is a multi-chip PLL receiver device supplied in an SO20 package. It has been especially de- veloped for the demands of RF low-cost data transmission systems with data rates from 1 kBaud to 10 kBaud in Manchester or Bi-phase code. The receiver is well suited to operate with the Atmel Wireless & ...
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... T5760 T5761 / Pin Description Pin Symbol Function 1 SENS Sensitivity-control resistor 2 IC_ IC condition indicator ACTIVE Low = sleep mode High = active mode 3 CDEM Lower cut-off frequency data fil- ter 4 AVCC Analog power supply 5 TEST 1 Test pin, during operation at GND 6 AGND Analog ground 7 n.c. Not connected, connect to GND ...
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... GND with a . The I/Q series capacitor C VCO mended by the crystal supplier. Due to a somewhat inductive impedance at steady state oscillation and some PCB parasitics a lower value of C Preliminary Information T5760 / T5761 Data – DATA interface POLLING/_ON and DATA_CLK CLK IC_ACTIVE ...
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... CM ( motional capacitance ) used, an additional XTO pulling of $30 ppm has to be added. The resulting total LO tolerance of $120ppm agrees with the receiving bandwidth specification T5760/T5761 if the T5750 has also a total LO tolerance of $120 ppm DVCC XTAL n.c. TEST 3 TEST 2 Figure 4 ...
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... XTO deviation of the T5760/T5761. Low- cost crystals are specified to be within 90 ppm over tolerance, temperature and aging. The XTO deviation of the T5760/T5761 is an additional deviation due to the st -order highpass and XTO circuit. This deviation is specified ppm worst case for a crystal with ...
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... T5760 T5761 / 0 –10 –20 –30 –40 –50 –60 –4 –3 –2 – MHz ) Figure 6. Narrow band receiving frequency response 0 –20 –40 –60 –80 –100 –12 –9 –6 – MHz ) Figure 7. Wide band receiving frequency response Polling Circuit and Control Logic ...
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... Sleep is programmed into the OPMODE register. This Sleep function is desirable where several devices share a single data line and may also be used for C polling – via Pin POLLING/_ON, the receiver can be switched on and off. Preliminary Information T5760 / T5761 + Sleep Startup Bit-check ...
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... T5760 T5761 / Sleep mode: All circuits for signal processing are disabled. Only XTO and Polling logic is enabled. Output level on Pin IC_ACTIVE => low Soff T = Sleep X 1024 T Sleep Sleep Start-up mode: The signal processing circuits are enabled. After the start-up time (T Startup are in stable condition and ready to receive. Output level on Pin IC_ACTIVE => ...
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... Lim_min and Lim_max at the occurrence of a signal edge. In figure 15 the bit check fails as the value CV_lim is lower than the limit Lim_min. The bit check also fails if CV_Lim reaches Lim_max. This is illustrated in . This is achieved us- figure 16. Preliminary Information T5760 / T5761 T XClk T XClk , T Lim_min Lim_min ...
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... T5760 T5761 / ( Lim_min = 14, Lim_max = 24 ) IC_ACTIVE Bit check Dem_out Bit–check– counter T Start–up Start–up mode ( Lim_min = 14, Lim_max = 24 ) IC_ACTIVE Bit check Dem_out Bit–check– counter T Start–up Start–up mode Figure 12. Timing diagram for failed bit check (condition: CV_Lim < Lim_min) ...
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... Dem_out remains Low after the receiver has switched to receiving mode DATA_min Figure 15. Debouncing of the demodulator output Receiving mode Bit–check mode Preliminary Information T5760 / T5761 T . This implies an effi- ee DATA_min . This function is employed to ensure is thereby longer DATA_L_max t DATA_min DATA_L_max ...
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... T5760 T5761 / After the end of a data transmission, the receiver remains active. Depending of the bit Noise_Disable in the OP- MODE register, the output signal at Pin DATA is high or random noise pulses appear at Pin DATA (see chapter ’Digital Noise Supression’). The edge-to-edge time pe- ...
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... Note that for Bi-phase-coded signals, the data clock is is- sued at the end of the bit. Preliminary Information T5760 / T5761 X X Receiving mode after the edge on Pin DATA (see fig- Delay 13 (32) ...
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... T5760 T5761 / Bit check ok ’1’ Dem_out Data_out (DATA) DATA_CLK Bit–check mode ’1’ Dem_out Data_out (DATA) DATA_CLK Receiving mode, data clock control logic active Figure 21. Data clock disappears because of a timing error ’1’ Dem_out Data_out (DATA) DATA_CLK Figure 22. Data clock disappears because of a logical error ...
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... Delay1 Interface’). 0, 0, Delay1 Delay2 t t Delay P_Data_Clk 0, 0, Delay1 Delay2 t t Delay P_Data_Clk Preliminary Information T5760 / T5761 ’1’ ’1’ ’0’ ’1’ ’0’ (32) ...
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... T5760 T5761 / Digital Noise Suppression After a data transmission, digital noise appears on the data output (see figure 26). To prevent that digital noise keeps the connected C busy, it can be suppressed in two differ- ent ways. 1. Automatic noise suppression: If the bit Noise_Disable (table 9) in the OPMODE register is set to 1 (default), the receiver changes to bit-check mode at the end of a valid data stream ...
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... This way to suppress the noise is recommended if the data stream is not Manchester or Bi-phase coded. Configuration of the Receiver The T5760/T5761 receiver is configured via two 12-bit RAM registers called OPMODE and LIMIT. The regis- ters can be programmed by means of the bidirectional DATA port. If the register contents have changed due to a voltage drop, this condition is indicated by a certain out- put pattern called reset marker (RM) ...
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... T5760 T5761 / Table 3 Effect of the configuration words within the registers Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 1 BR_Range N Bit–check 0 1 Baud1 Baud0 BitChk 1 É É É É É É É É É É É É É É É É Default É ...
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... Noise suppression is active (default) É É É É É É É É É É É É É É É É É É É É Preliminary Information T5760 / T5761 Selected Modulation FSK ASK y ...
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... Lim_max is also be used to determine the margins of the data clock control logic (see chapter ’Data Clock’) Conservation of the Register Information The T5760/T5761 implies an integrated power-on reset and brown-out detection circuitry to provide a mecha- nism to preserve the RAM register information. According to figure 30, a power–on reset (POR) is gener- ...
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... Figure 31. Timing of the register programming T5760/ T5761 R pup DATA 0 ... 20 V Serial bi–directional data line Figure 32. Data interface Preliminary Information T5760 / T5761 Bit 14 Bit 15 (”0”) (”0”) (Poll8) (Stop bit) T Sleep T Start–up Start–up Sleep mode mode C I/O ...
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... T5760 T5761 / To start programming, the serial data line DATA is pulled to Low for the time period t1 by the C. When DATA has been released, the receiver becomes the master device. When the programming delay period t2 has elapsed, it emits 15 subsequent synchronization pulses with the pulse length t3 ...
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... C17 5.6p 18p 5% 5% np0 np0 Toko LL2012 F5N6J 5.6 nH OUT 6 OUT_GND CASE_GND 7 CASE_GND 8 = 868.3 MHz with SAW filter RF Preliminary Information T5760 / T5761 IC_ACTIVE Sensitivity reduction >= 1.6k DATA POLLING/_ON DATA_CLK C12 10n 10% Q1 C11 12p np0 2% IC_ACTIVE Sensitivity reduction ...
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... T5760 T5761 / Absolute Maximum Ratings Parameter Supply voltage Power dissipation Junction temperature Storage temperature Ambient temperature Maximum input level, input matched Thermal Resistance Parameter Junction ambient Electrical Characteristics All parameters refer to GND – +105 C, V amb less otherwise specified. (For typical values: V ...
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... Preliminary Information T5760 / T5761 = 868.3 MHz and f = 915 MHz, un Variable Oscillator Max. Min. Typ. Max. f 128 / 867.3 XTO 1.89 BR_Range0 Clk 3.38 BR_Range1 Clk 5.9 BR_Range2 Clk 10.5 BR_Range3 Clk 156.8 10 ...
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... T5760 T5761 / Electrical Characteristics (continued) All parameters refer to GND – +105 C, V amb less otherwise specified. (For typical values: V Parameter Test Conditions Symbol Configuration of the receiver (see figures 17 and 33) Freque Frequency is ncy of the re- stable within set marker 50 ms after POR ...
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... IS LORF NF Zi LNA_IN IP 1db – in_max f VCO f VCO L (fm XTO Preliminary Information T5760 / T5761 = 868.3 MHz and f = 915 MHz, un Min. Typ. Max. 170 276 7.8 9.9 7.4 9.6 IN –16 –70 –57 5 200 || 3.2 200 || 3.2 – –10 –10 866 871 ...
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... T5760 T5761 / Electrical Characteristics (continued) All parameters refer to GND – +105 C, V amb less otherwise specified. (For typical values: V Parameters Test Conditions / Pins Analog signal processing (input matched according to figure 33 referred to RF Input sensitivity ASK ASK (level of carrier) BERv10 f = 868.3 MHz / 915 MHz ...
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... MHz Ref_Red P Ref_Red DP Red + DP Ref_Red Red DP Red DP Red DP Red DP Red DP Red DP Red + DP Ref_Red Red V ThRESET Preliminary Information T5760 / T5761 = 868.3 MHz and f = 915 MHz, un Min. Typ. Max 0.11 0.16 0. 8.2 270 1000 156 560 89 320 50 180 2.8 3.4 4.0 4.8 6 ...
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... T5760 T5761 / Electrical Characteristics (continued) All parameters refer to GND – +105 C, V amb less otherwise specified. (For typical values: V Parameters Test Conditions / Pins Digital ports Data output – Saturation voltage Low – max voltage @ Pin DATA – ...
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... Package Information Package SO20 Dimensions in mm 12.95 12.70 0.4 1.27 11. Rev. A2, 19-Oct-00 2.35 0.25 0.10 11 technical drawings according to DIN specifications 10 Preliminary Information T5760 / T5761 9.15 8.65 7.5 7.3 0.25 10.50 10.20 13038 31 (32) ...
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... T5760 T5761 / Ozone Depleting Substances Policy Statement It is the policy of Atmel Germany GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment ...