X24645P-2.7 XICOR [Xicor Inc.], X24645P-2.7 Datasheet - Page 5

• Manufacturer Part Number: X24645P-2.7
• Description: Advanced 2-Wire Serial E 2 PROM with Block Lock TM Protection
• Manufacturer: XICOR [Xicor Inc.]

X24645
Figure 5. Byte Write
DEVICE ADDRESSING
Following a start condition the master must output the
address of the slave it is accessing (see Figure 4). The
next two bits are the device select bits. A system could
have up to four X24645’s on the bus. The four
addresses are defined by the state of the S
inputs. S
the S
Figure 4. Slave Address
The next five bits of the slave address are an exten-
sion of the array’s address and are concatenated with
the eight bits of address in the byte address field,
providing direct access to the whole 8192 x 8 array.
2
input pin.
S 2
2
SELECT
DEVICE
of the slave address must be the inverse of
S 1
A12
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
X24645
A11 A10
HIGH ORDER
ADDRESS
BITS
A9
S
S
A
R
T
T
2783 ILL F07.1
A8
ADDRESS
SLAVE
R/W
1
and S
2
C
A
K
5
The last bit of the slave address defines the operation to
be performed. When set HIGH a read operation is
selected, when set LOW, a write operation is selected.
Following the start condition, the X24645 monitors the
SDA bus comparing the slave address being transmitted
with its slave address device type identifier. Upon a
correct compare the X24645 outputs an acknowledge on
the SDA line. Depending on the state of the R/W bit, the
X24645 will execute a read or write operation.
WRITE OPERATIONS
Byte Write
For a write operation, the X24645 requires a second ad-
dress field. This address field is the byte address, com-
prised of eight bits, providing access to any one of 8192
words in the array. Upon receipt of the byte address, the
X24645 responds with an acknowledge and awaits the
next eight bits of data, again responding with an acknowl-
edge. The master then terminates the transfer by gener-
ating a stop condition, at which time the X24645 begins
the internal write cycle to the nonvolatile memory. While
the internal write cycle is in progress the X24645 inputs
are disabled, and the device will not respond to any re-
quests from the master. Refer to Figure 5 for the address,
acknowledge and data transfer sequence.
ADDRESS
BYTE
A
C
K
DATA
2783 ILL F08.1
C
A
K
P
S
O
P
T