MFR4200MAE40 FREESCALE [Freescale Semiconductor, Inc], MFR4200MAE40 Datasheet - Page 113
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MFR4200MAE40
Manufacturer Part Number
MFR4200MAE40
Description
FlexRay Communication Controllers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MFR4200MAE40.pdf
(260 pages)
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3.2.3.6.4
FlexRay Protocol Related Parameter – vClockCorrectionFailed
Address 0x326
Reset
This register holds the clock correction failed counter. This counter is reset when a node enters normal
active operation. It is incremented by one at the end of any odd communication cycle, when either the
missing offset correction error or the missing rate correction error, or both, are active. The counter is reset
to zero at the end of an odd communication cycle if neither the offset correction failed error nor the rate
correction failed error is active. The counter is not incremented after it reaches the maximum odd
communication cycles without clock correction programmed value (see
Odd Cycles Without Clock Correction Fatal Register
this register.
3.2.3.6.5
Address 0x328
Reset
This register holds the current value of the error handling level. Error handling levels are defined in
Table
Freescale Semiconductor
Reserved
Reserved
Reserved
Reserved
15
15
7
7
r
r
r
r
3-7:
undefined state
undefined state
Clock Correction Failed Counter Register (CCFCR)
Error Handling Level Register (EHLR)
Reserved
Reserved
Reserved
Reserved
14
14
6
6
r
r
r
r
Figure 3-76. Clock Correction Failed Counter Register
Reserved
Reserved
Reserved
Reserved
Figure 3-77. Error Handling Level Register
13
13
5
5
r
r
r
r
MFR4200 Data Sheet, Rev. 0
Reserved
Reserved
Reserved
Reserved
12
12
4
4
r
r
r
r
(MOCWCFR)”). The host has read-only access to
Reserved
Reserved
Reserved
OWCC3
11
11
rh
3
3
r
r
r
Reserved
Reserved
Reserved
OWCC2
10
10
rh
Section 3.2.3.5.2, “Maximum
2
2
r
r
r
Reserved
Reserved
OWCC1
Memory Map and Registers
EHL1
rh
rh
9
1
9
1
r
r
Reserved
Reserved
OWCC0
EHL0
rh
rh
8
0
8
0
r
r
113
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