MFR4200MAE40 FREESCALE [Freescale Semiconductor, Inc], MFR4200MAE40 Datasheet - Page 126
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MFR4200MAE40
Manufacturer Part Number
MFR4200MAE40
Description
FlexRay Communication Controllers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MFR4200MAE40.pdf
(260 pages)
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MFR4200 FlexRay Communication Controller
3.2.3.7.2
Address BUFCS0R=0x200, BUFCS1R=0x204, …, BUFCS57R=0x2E4, BUFCS58R=0x2E8.
BUFCSnR=0x200 + 0x4*dec2hex(n)
Reset
For a description of these registers and the bit access scheme, see
Configuration and Status
3.2.3.7.3
Address 0x180
Reset
For a description of this register and the bit access scheme, refer to
and
126
Reserved
VALID
Operations”.
ID7
rw*
15
15
R*
rw
7
7
*
r
IFLG, IENA, CFG and VALID bits are reset to 0, others – in undefined state
undefined state
Figure 3-90. Message Buffer Control, Configuration and Status n Register, n = [0:58]
Message Buffer Control, Configuration and Status n Register, n = [0:58]
(BUFCSnR)
Active Transmit Buffer Frame ID Register (ATBFRID)
LOCK
ID6
rw*
rw*
PP
TT
14
14
6
6
*
*
Register”.
Figure 3-91. Active Transmit Buffer Frame ID Register
Reserved
CCFE
NFI
ID5
rw*
13
13
5
5
*
r
r
MFR4200 Data Sheet, Rev. 0
Reserved
SYNC
ID4
rw*
BT
12
12
4
4
*
r
r
STARTUP
DATUPD
IENA
ID3
rw*
11
11
3
3
*
*
r
Section 3.4.1, “Message Buffer Control,
Section 3.5, “Message Buffer Handling
IFLG
CHB
ID10
ID2
rw*
rw*
10
10
2
2
*
*
Reserved
Freescale Semiconductor
CHA
ID9
ID1
rw*
rw*
9
1
9
1
*
r
BUFCMT
CFG
ID8
ID0
rw*
rw*
8
0
8
0
*
*
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