M38197 Mitsubishi, M38197 Datasheet - Page 40

• Manufacturer Part Number: M38197
• Description: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
• Manufacturer: Mitsubishi

INTERRUPT INTERVAL DETERMINATION
FUNCTION
The 3819 group builds in an interrupt interval determination circuit.
This interrupt interval determination circuit has an 8-bit binary up
counter. Using this counter, it determines a duration of time from
the rising transition (falling transition) of an input signal pulse on
the P4
signal pulse that is input next.
How to determine the interrupt interval is described below.
Fig. DE-1 Block diagram of interrupt interval datermination circuit
40
Enable the INT
trol register 1 (address 003E
falling interval by setting the bit 2 of the interrupt edge selection
register (address 003A
ter (address 0031
operating).
Select the sampling clock of 8-bit binary up counter by setting
the bit 1 of the interrupt interval determination control register.
When writing “0”, f(X
32 s at f(X
sampling interval: 64 s at f(X
When the signal of polarity which is set on the INT
falling transition) is input, the 8-bit binary up counter starts
counting up of the selected counter sampling clock.
When the signal of polarity above
the 8-bit binary up counter is transferred to the interrupt interval
Set the bit 0 of the interrupt interval determination control regis-
2
/INT
INT
2
2
IN
pin to the rising transition (falling transition) of the
interrupt input
) = 8.38 MHz) ; when “1”, f(X
2
Noise filter sampling
clock selection bit
interrupt by setting the bit 2 of the interrupt con-
16
) to “1” (interrupt interval determination
IN
16
)/256 is selected (the sampling interval:
).
The counter
sampling clock
selection bit
IN
16
) = 8.38 MHz).
1/64 1/128
). Select the rising interval or
Divider
f(X
is input again, the value of
Noise filter
IN
)
IN
1/256
)/512 is selected (the
f(X
f(X
One-sided/both-sided
detection selection bit
IN
IN
)/256
)/512
2
pin (rising or
8-bit binary up counter
Noise filter
The P4
The noise filter operation is described below.
Note : In the low-speed mode (CM
Interrupt interval
determination register
determination register (address 0030
interrupt request occurs. Immediately after that, the 8-bit binary
up counter is cleared to “00
tinues to count up again from “00
When count value reaches “FF
stops counting up. Then, simultaneously when the next counter
sampling clock is input, the counter sets value “FF
terrupt interval determination register to generate the counter
overflow interrupt request.
Select the sampling clock of the input signal with the bits 2 and
3 of the interrupt interval determination control register. When
not using the noise filter, set “00
The P4
selected clock. When sampling the same level signal in series,
the signal is recognized as the interrupt signal, and the interrupt
request occurs.
When setting the bit 4 of interrupt interval determination control
register to “1”, the interrupt request can occur at both rising and
falling edges.
When using the noise filter, set the minimum pulse width of the
INT
Data bus
2
function can not operate.
input signal to 2 cycles or more.
2
/INT
2
/INT
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
address 0030
2
pin builds in the noise filter.
2
input signal is sampled in synchronization with the
MITSUBISHI MICROCOMPUTERS
16
16
7
”. The 8-bit binary up counter con-
=1), the interrupt interval determination
The counter overflow
interrupt request or
remote control interrupt request
2
16
16
”.
”, the 8-bit binary up counter
”.
16
), and the remote control
3819 Group
16
” to the in-