BT8222EPFF CONEXANT [Conexant Systems, Inc], BT8222EPFF Datasheet - Page 28

• Manufacturer Part Number: BT8222EPFF
• Description: ATM Transmitter/Receiver with UTOPIA Interface
• Manufacturer: CONEXANT [Conexant Systems, Inc]

1.0 Product Description
1.9 Logic Diagram
Figure 1-11. CN8223 Logic Diagram
1-18
Transmit Clock In PECL
One-Second Clock Sync
Receive Serial In PECL
Receive Clock In PECL
Transmit Clock Input
8/16-Bit Mode Select
Receive Clock Input
Transmit Overhead
Processor Data Bus
Receiver Hold Input
Write/Read Control
FIFO Control Input
8 kHz Clock Input
FIFO Data Bus In
Processor Clock
Address Strobe
Transmit Input
Receive Input
Output Enable
Address Bus
Chip Select
Test Inputs
Test Input
Bus In
Reset
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I 117,
I
154,155
109–116
98–105,
15–19,
68–79,
82–84
44–51
85–91
11,12
20,21
22,25
23,24
119
123
118
108
65,
97
96
94
95
92
37
62
61
59
10
30
32
RXCKI
RXCKI_HS
RXIN_HS
RXIN[8:0]
TXCKI
TXCKI_HS
TXIN
TXOVH[7:0]
FDAT_IN[8:0]
FCTRL_IN[7:0]
SEL8BIT
PRCLK
CS
AS
W/R
OE
D[15:0]
A[7:1]
8KCKI
ONESECI
RCV_HLD
NTEST
TEST1, TEST3
RESET
~
~
~
~
I = Input, O = Output
±
Framing Overhead
Clock and Control
Line Framer/PHY
±
±
UTOPIA/FIFO
Microprocessor
Interface
Conexant
Interface
Interface
Interface
FCTRL_OUT[16:0]
ROVH_CLK[1:0]
FDAT_OUT[8:0]
TCLKO_HS
TXOUT_HS
RMRKR[1:0]
RXOVH[7:0]
TXOUT[8:0]
TOVH_CLK
ONESECO
STAT_INT
ATM Transmitter/Receiver with UTOPIA Interface
TMRKR
DL_INT
TCLKO
LOCD
±
±
31
33–36,
42,43,
56–58
28,29
38,39
122
2–5,
156–159
8,9
6,7
55
52
143–145,
148–153
124–132,
135–142
63
64
60
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O One-Second Output
Receive Overhead Bus Out
Receive Overhead Markers
Receive Overhead Clocks
Transmit Overhead Clock
Transmit Overhead Marker
Transmit Clock Output
Transmit Outputs
Transmit Clock Out PECL
Transmit Serial Out PECL
Loss of Cell Delineation
FIFO Data Bus Out
FIFO Control Outputs
FEAC/HDLC Interrupt
Status/Counter Interrupt
100046C
CN8223