EM78156EAS EMC [ELAN Microelectronics Corp], EM78156EAS Datasheet - Page 20

• Manufacturer Part Number: EM78156EAS
• Description: 8-Bit Microcontroller with MASK ROM
• Manufacturer: EMC [ELAN Microelectronics Corp]

EM78156E
8-Bit Microcontroller with MASK ROM
3
16 •
NOTE: Vdd = 5V, set up time period = 16.8ms ± 30%
Vdd = 3V, set up time period = 18ms ± 30%
(2) /RESET pin input "low",or
(3) WDT time-out (if enabled).
The device is kept in a RESET condition for a period of approx. 18
start-up timer period) after the reset is detected. Once the RESET occurs, the following
functions are performed. Refer to Fig.9.
The sleep (power down) mode is asserted by executing the “SLEP” instruction. While
entering sleep mode, WDT (if enabled) is cleared but keeps on running. The controller
can be awakened by-
(1) External reset input on /RESET pin,
(2) WDT time-out (if enabled), or
(3) Port 6 input status changes (if enabled).
The first two cases will cause the EM78156E to reset. The T and P flags of R3 can be
used to determine the source of the reset (wake-up). The last case is considered the
continuation of program execution and the global interrupt ("ENI" or "DISI" being
executed) decides whether or not the controller branches to the interrupt vector
following wake-up. If ENI is executed before SLEP, the operation will restart from the
succeeding instruction right next to SLEP after wake-up.
Only one of Cases 2 and 3 can be enabled before entering the sleep mode. That is,
[a] if Port 6 Input Status Change Interrupt is enabled before SLEP , WDT must be
disabled. by software. However, the WDT bit in the option register remains
enabled. Hence, the EM78156E can be awakened only by Case 1 or 3.
The oscillator is running, or will be started.
The Program Counter (R2) is set to all "0".
All I/O port pins are configured as input mode (high-impedance state).
The Watchdog timer and prescaler are cleared.
When power is switched on, the upper 3 bits of R3 are cleared.
The bits of the CONT register are set to all "1" except for the Bit 6 (INT flag).
The bits of the IOCA register are set to all "1".
The bits of the IOCB register are set to all "1".
The IOCC register is cleared.
The bits of the IOCD register are set to all "1".
Bit 7 of the IOCE register is set to "1", and Bits 4 and 6 are cleared.
Bits 0~2 of RF and bits 0~2 of IOCF register are cleared.
(This specification is subject to change without further notice)
Product Specification (V1.3) 07.29.2004
3
ms (one oscillator