EP910 ALTERA [Altera Corporation], EP910 Datasheet - Page 9

• Manufacturer Part Number: EP910
• Description: The Altera Classic device family offers a solution to high-speed, lowpower logic integration. Fabricated on advanced CMOS technology
• Manufacturer: ALTERA [Altera Corporation]

Altera Corporation
Turbo Bit
Option
Generic Testing
Device
Programming
Many Classic devices contain a programmable Turbo Bit
control the automatic power-down feature that enables the low-standby-
power mode. When the Turbo Bit option is turned on, the low-standby-
power mode is disabled. All AC values are tested with the Turbo Bit
option turned on. When the device is operating with the Turbo Bit option
turned off (non-Turbo mode), a non-Turbo adder must be added to the
appropriate AC parameter to determine worst-case timing. The non-
Turbo adder is specified in the “AC Operating Conditions” tables for each
Classic device that supports the Turbo mode.
Classic devices are fully functionally tested. Complete testing of each
programmable EPROM configuration element and all internal logic
elements before and after packaging ensures 100% programming yield.
See
contain on-board logic test circuitry to allow verification of function and
AC specifications during standard production flow.
Figure 6. AC Test Conditions
Classic devices can be programmed on 486- and Pentium-based PCs with
the MAX+PLUS II Programmer, an Altera Logic Programmer card, the
MPU, and the appropriate device adapter. The MPU performs continuity
checking to ensure adequate electrical contact between the adapter and
the device.
Data I/O, BP Microsystems, and other programming hardware
manufacturers also offer programming support for Altera devices. See
Programming Hardware Manufacturers
Power-supply transients can affect AC
measurements. Simultaneous transitions of
multiple outputs should be avoided for
accurate measurement. Threshold tests
must not be performed under AC
conditions. Large-amplitude, fast ground-
current transients normally occur as the
device outputs discharge the load
capacitances. When these transients flow
through the parasitic inductance between
the device ground pin and the test system
ground, significant reductions in observable
noise immunity can result.
Figure 6
for AC test measurement conditions. These devices also
for more information.
Device
Output
Classic EPLD Family Data Sheet
885
340
R1
R2
TM
C1 (includes
JIG capacitance)
option to
VCC
System
To T est
753