MX25L3225DM2I-10G MCNIX [Macronix International], MX25L3225DM2I-10G Datasheet - Page 25

• Manufacturer Part Number: MX25L3225DM2I-10G
• Description: 32M-BIT [x 1/x 2/x 4] CMOS SERIAL FLASH
• Manufacturer: MCNIX [Macronix International]

P/N: PM1432
Table 8. Security Register Definition
(22) Write Security Register (WRSCUR)
The WRSCUR instruction is for changing the values of Security Register Bits. Unlike write status register, the WREN
instruction is not required before sending WRSCUR instruction. The WRSCUR instruction may change the values of bit1
(LDSO bit) for customer to lock-down the 4K-bit Secured OTP area. Once the LDSO bit is set to "1", the Secured OTP
area cannot be updated any more.
The sequence of issuing WRSCUR instruction is :CS# goes low-> sending WRSCUR instruction -> CS# goes high.
The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.
volatile bit
reserved
bit7
x
volatile bit
reserved
bit6
x
volatile bit
reserved
bit5
x
Program mode
Program mode
Continuously
1=CP mode
(CP mode)
(default=0)
volatile bit
0=normal
bit4
25
volatile bit
reserved
bit3
x
volatile bit
reserved
bit2
MX25L3225D
x
program/erase
non-volatile bit non-volatile bit
1 = lock-down
0 = not lock-
(indicate if
lock-down
(cannot
LDSO
OTP)
down
bit1
REV. 0.00, SEP. 19, 2008
Secrured OTP
indicator bit
factory lock
1 = factory
0 = non-
lock
bit0