BC41B143A-ds-001Pe CSR, BC41B143A-ds-001Pe Datasheet - Page 54

• Manufacturer Part Number: BC41B143A-ds-001Pe
• Description: Blue Core ROM
• Manufacturer: CSR

10.2
The BlueCore4-ROM RF local oscillator and internal digital clocks are derived from the reference clock at the
BlueCore4-ROM XTAL_IN input. This reference may be either an external clock or from a crystal connected
between XTAL_IN and XTAL_OUT. The crystal mode is described in Section 10.2.5.
10.2.1 External Mode
BlueCore4-ROM can be configured to accept an external reference clock (from another device, such as TCXO)
at XTAL_IN by connecting XTAL_OUT to ground. The external clock can either be a digital level square wave or
sinusoidal and this may be directly coupled to XTAL_IN without the need for additional components. If the peaks
of the reference clock are below VSS_ANA or above VDD_ANA, it must be driven through a DC blocking
capacitor (~33pF) connected to XTAL_IN. A digital level reference clock gives superior noise immunity as the
high slew rate clock edges have lower voltage to phase conversion.
The external clock signal should meet the specifications in Table 10.2:
Notes:
10.2.2 XTAL_IN Impedance in External Mode
The impedance of the XTAL_IN will not change significantly between operating modes, typically 10fF. When
transitioning from deep sleep to an active state a spike of up to 1pC may be measured. For this reason it is
recommended that a buffered clock input be used.
10.2.3 Clock Timing Accuracy
As Figure 10.4 indicates, the 250ppm timing accuracy on the external clock is required 7ms after the assertion of
the system clock request line. This is to guarantee that the firmware can maintain timing accuracy in accordance
with the Bluetooth v2.0 specification. Radio activity may occur after 11ms, therefore at this point, the timing
accuracy of the external clock source must be within 20ppm.
Frequency
Duty cycle
Edge Jitter (At Zero Crossing)
Signal Level
BC41B143A-ds-001Pe
(1)
(2)
(3)
The frequency should be an integer multiple of 250kHz except for the CDMA/3G frequencies
VDD_ANA is 1.8V nominal
If the external clock is driven through a DC blocking capacitor then maximum allowable amplitude is
reduced from VDD_ANA to 800mV pk-pk
External Reference Clock Input (XTAL_IN)
(1)
CLK_REQ
0
This material is subject to CSR’s non-disclosure agreement
Table 10.2: External Clock Specifications
Figure 10.4: TCXO Clock Accuracy
© Cambridge Silicon Radio Limited 2005
Required TCXO Clock Accuracy
ms After Clock Request
Production Information
400mV pk-pk
7.5MHz
20:80
1000 ppm
Min
-
5
250 ppm
7
16MHz
50:50
Typ
-
-
Device Terminal Descriptions
20 ppm
11
VDD_ANA
15ps rms
Page 54 of 102
40MHz
80:20
Max
(2)(3)