ZL10036LDF ZARLINK [Zarlink Semiconductor Inc], ZL10036LDF Datasheet - Page 24

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ZL10036LDF

Manufacturer Part Number
ZL10036LDF
Description
Digital Satellite Tuner with RF Bypass
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
3.4.7
The RF bypass function is disabled by setting LEN, bit-0 of register byte-4 to a logic ‘1’. By default, this bit is at a
logic ‘0’ at power-up, and therefore the function is enabled. If the function is not required, a power saving of
approximately 15% can be made by setting this bit. See also section 2.3 on page 16.
3.4.8
Register bits P1 and P0, bit-7 in register bytes-7 & 5 respectively, control the output port pins, P1 & P0, pin numbers
39 & 24 respectively.
3.4.9
Bit-7 of byte-13 controls the PD register bit which is an alternative to the SLEEP pin (see “SLEEP - Pin 11” on
page 19). Setting the PD bit to a logic ‘1’ shuts down the analogue sections of the ZL10036 effecting a saving of
about two thirds of the power required for normal operation. A logic ’0’ restores normal operation. With either
hardware or software power-down, all register settings are unaffected.
3.4.10
Bit-1 of byte-13 controls the CLR register bit. When set to a logic ‘1’, this self-clearing bit resets the ZL10036 control
logic. Writing a logic ‘0’ has no effect. The following register numbers are reset to their power-on state: 7, 9, 10, 11,
12 & 13. All other register’s contents are unaffected.
3.4.11
Register bits C1 and C0 are programmed by setting bits-6 & 5 of register byte-5. These bits determine the charge
pump current that is used on the output of the frequency synthesizer phase detector.
RF Bypass Disable (LEN Bit)
Output Port Controls (P1 & P0 Bits)
Power Down (PD Bit)
Charge Pump Current (C1 & C0 Bits)
Logic Reset (CLR Bit)
Bit P1 or P0
0
1
C1
0
0
1
1
Table 12 - Charge Pump Currents
C0
High impedance
Low impedance to Vee (Gnd)
0
1
0
1
Min.
±160
±280
±470
Table 11 - Port Control Bits
Port State
Zarlink Semiconductor Inc.
Current in µA
Not allowed
ZL10036
Typ.
±210
±365
±625
24
Max.
±290
±510
±860
(if connected to a pull-up)
1
0
(reset state)
Logic State
(reset state)
Data Sheet

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