OR2C15A-7J240 ETC [List of Unclassifed Manufacturers], OR2C15A-7J240 Datasheet

OR2C15A-7J240

Manufacturer Part Number

OR2C15A-7J240

Description

Field-Programmable Gate Arrays

Manufacturer

ETC [List of Unclassifed Manufacturers]

Datasheet

1.OR2C15A-7J240.pdf (192 pages)

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June 1999

Features

Table 1 . ORCA Series 2 FPGAs

* The first number in the usable gates column assumes 48 gates per PFU (12 gates per four-input LUT/FF pair) for logic-only designs. The

OR2C15A/OR2T15A/OR2T15B

OR2C40A/OR2T40A/OR2T40B

second number assumes 30% of a design is RAM. PFUs used as RAM are counted at four gates per bit, with each PFU capable of

implementing a 16 x 4 RAM (or 256 gates) per PFU.

High-performance, cost-effective, low-power

0.35 µm CMOS technology (OR2CxxA), 0.3 µm CMOS

technology (OR2TxxA), and 0.25 µm CMOS technology

(OR2TxxB), (four-input look-up table (LUT) delay less

than 1.0 ns with -8 speed grade)

High density (up to 43,200 usable, logic-only gates; or

99,400 gates including RAM)

Up to 480 user I/Os (OR2TxxA and OR2TxxB I/Os are

5 V tolerant to allow interconnection to both 3.3 V and

5 V devices, selectable on a per-pin basis)

Four 16-bit look-up tables and four latches/flip-flops per

PFU, nibble-oriented for implementing 4-, 8-, 16-, and/or

32-bit (or wider) bus structures

Eight 3-state buffers per PFU for on-chip bus structures

Fast, on-chip user SRAM has features to simplify RAM

design and increase RAM speed:

— Asynchronous single port: 64 bits/PFU

— Synchronous single port: 64 bits/PFU

— Synchronous dual port: 32 bits/PFU

Improved ability to combine PFUs to create larger RAM

structures using write-port enable and 3-state buffers

Fast, dense multipliers can be created with the multiplier

mode (4 x 1 multiplier/PFU):

— 8 x 8 multiplier requires only 16 PFUs

— 30% increase in speed

Flip-flop/latch options to allow programmable priority of

synchronous set/reset vs. clock enable

Enhanced cascadable nibble-wide data path

capabilities for adders, subtractors, counters, multipliers,

and comparators including internal fast-carry operation

OR2C04A/OR2T04A

OR2C06A/OR2T06A

OR2C08A/OR2T08A

OR2C10A/OR2T10A

OR2C12A/OR2T12A

OR2C26A/OR2T26A

Device

12,300—28,300

15,600—35,800

19,200—44,200

27,600—63,600

43,200—99,400

4,800—11,000

6,900—15,900

9,400—21,600

Usable

Gates*

# LUTs

1024

1296

1600

2304

3600

400

576

784

Field-Programmable Gate Arrays

* IEEE is a registered trademark of The Institute of Electrical and

Electronics Engineers, Inc.

Innovative, abundant, and hierarchical nibble-

oriented routing resources that allow automatic use of

internal gates for all device densities without sacrificing

performance

Upward bit stream compatible with the ORCA ATT2Cxx/

ATT2Txx series of devices

Pinout-compatible with new ORCA Series 3 FPGAs

TTL or CMOS input levels programmable per pin for the

OR2CxxA (5 V) devices

Individually programmable drive capability:

12 mA sink/6 mA source or 6 mA sink/3 mA source

Built-in boundary scan ( IEEE *1149.1 JTAG) and

3-state all I/O pins, (TS_ALL) testability functions

Multiple configuration options, including simple, low pin-

count serial ROMs, and peripheral or JTAG modes for in-

system programming (ISP)

Full PCI bus compliance for all devices

Supported by industry-standard CAE tools for design

entry, synthesis, and simulation with ORCA Foundry

Development System support (for back-end implementa-

tion)

New, added features (OR2TxxB) have:

— More I/O per package than the OR2TxxA family

— No dedicated 5 V supply (V

— Faster configuration speed (40 MHz)

— Pin selectable I/O clamping diodes provide 5V or 3.3V

— Full PCI bus compliance in both 5V and 3.3V PCI sys-

PCI compliance and 5V tolerance

tems

Registers

1024

1296

1600

2304

3600

400

576

724

Max User

RAM Bits

12,544

16,384

20,736

25,600

36,864

57,600

6,400

9,216

ORCA

User

I/Os

160

192

224

256

288

320

384

480

Series 2

Array Size

10 x 10

12 x 12

14 x 14

16 x 16

18 x 18

24 x 24

20 x 20

30 x 30

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