L7C108 LODEV [LOGIC Devices Incorporated], L7C108 Datasheet

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L7C108

Manufacturer Part Number
L7C108
Description
128K x 8 Static RAM
Manufacturer
LODEV [LOGIC Devices Incorporated]
Datasheet
1.L7C108.pdf (15 pages)
The L7C108 and L7C109 are high-perfor-
mance, low-power CMOS static RAMs.
The storage circuitry is organized as
131,072 words by 8 bits per word. The
8 Data In and Data Out signals share I/O
pins. The L7C108 has a single active-
low Chip Enable. The L7C109 has two
Chip Enables one active-low . These
devices are available in three speeds
with maximum access times from 15 ns
to 45 ns.
Inputs and outputs are TTL compatible.
Operation is from a single +5 V power
supply. Power consumption is 140 mA
retained in inactive storage with a supply
voltage as low as 2 V.
The L7C108 and L7C109 provide asyn-
chronous
matching access and cycle times. The
LOGIC Devices Incorporated
-L Version at 15 ns.
FEATURES
OVERVIEW
128K x 8 Static RAM with Chip
Select Powerdown, Output Enable
High Speed — to 15 ns maximum
Operational Power, -L Version
Active: 140 mA at 15 ns
Standby: 1 mA max
Data Retention at 2 V for Battery
Backup Operation
and Single or Dual Chip Selects
Screened to MIL-STD-883, Class B
or to SMD 5962-89598
Package Styles Available:
32-pin Ceramic 400mil DIP D12
32-pin Ceramic LCC K11
32-pin Ceramic SO
32-pin
unclocked
uad Ceramic LCC KA1
operation with
www.logicdevices.com
Data may be
1
Chip Enables and a three-state I/O bus
with a separate Output Enable control
simplify the connection of several chips
for increased storage capacity.
Memory locations are specified on
address pins A
L7C108, reading from a designated
location is accomplished by present-
ing an address and driving CE
LOW while WE remains HIGH. For the
L7C109, CE
while CE
the addressed memory location will then
appear on the Data Out pins within one
access time. The output pins stay in a
high-impedance state when CE
HIGH, or CE
Writing to an addressed location is
accomplished when the active-low CE
and WE inputs are both LOW, and CE
L7C109 is HIGH. Any of these signals
DQ
DQ
DQ
Pin Configuration
32-pin Ceramic SOJ
V
32-pin Ceramic DIP
A
A
A
NC
A
A
A
A
A
A
A
A
SS
16
14
12
7
6
5
4
3
2
1
0
1
2
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
2
and WE are HIGH.The data in
2
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
L7C109 or WE is LOW.
and OE must be LOW
0
through A
1
V
A
CE
WE
A
A
A
A
OE
A
CE
DQ
DQ
DQ
DQ
DQ
CC
15
13
8
9
11
10
2
8
7
6
5
4
16
DQ
A
A
A
A
A
A
A
A
. For the
7
6
5
4
3
2
1
0
1
1
1
or OE is
and OE
5
6
7
8
9
10
11
12
13
32-pin Quad CLCC
14
4
15 16 17 18
3
1
2
2
View
Top
1
PRELIMINARY INFORMATION
32
may be used to terminate the write oper-
ation. Data In and Data Out signals have
the same polarity.
Latchup and static discharge protection
are provided on-chip. The L7C108 and
L7C109 can withstand an injection cur-
rent of up to 200 mA on any pin without
damage.
31
19 20
30
29
28
27
26
25
24
23
22
21
WE
A
A
A
A
OE
A
CE
DQ
13
8
9
11
10
1
8
128K x 8 Static RAM
DQ
DQ
DQ
V
A
A
A
NC
32-pin Ceramic LCC
A
A
A
A
A
A
A
A
SS
16
14
12
7
6
5
4
3
2
1
0
1
2
3
Aug 11, 2010 LDS-L7C108/9-F
1M Static RAMs
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
L7C108
L7C109
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
A
CE
WE
A
A
A
A
OE
A
CE
DQ
DQ
DQ
DQ
DQ
CC
15
13
8
9
11
10
2
8
7
6
5
4

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L7C108 Summary of contents

Page 1

... CMOS static RAMs. The storage circuitry is organized as 131,072 words by 8 bits per word. The 8 Data In and Data Out signals share I/O pins. The L7C108 has a single active- low Chip Enable. The L7C109 has two Chip Enables one active-low . These devices are available in three speeds with maximum access times from ...

Page 2

... Static RAM 128 I High - High - High - High - High - Static RAMs Aug 11, 2010 LDS-L7C108/9-F L7C108 L7C109 POWER Standby I CC2 Standby I CC2 Standby I CC3 Standby I CC3 Active Active Active ...

Page 3

... Vcc 2.2 2.2 Vcc +0.5 +0.3 -0.5 0.8 -3.0 +10 -10 -10 +10 -10 +10 - L7C108/109 L7C108/109 140 140 135 125 140 140 140 130 1M Static RAMs Aug 11, 2010 LDS-L7C108/9-F L7C108 L7C109 Unit 0.8 μA μ Unit 125 mA ...

Page 4

... DATA VALID t EHQZ t GHQZ HIGH IMPEDANCE DATA VALID 50% 1M Static RAMs Aug 11, 2010 LDS-L7C108/9-F L7C108 L7C109 Max Min Max ...

Page 5

... Max Min Max Min Max Max Static RAMs Aug 11, 2010 LDS-L7C108/9-F Min Max 45 0 Min Max ...

Page 6

... DVWH DATA -IN VALID t WLQZ HIGH IMPEDANCE Notes 16, 17, 18 AVAV t AELWH t AVWH t WLWH t DVWH DATA-IN VALID HIGH IMPEDANCE PRELIMINARY INFORMATION 128K x 8 Static RAM t WHAX t WHDX t WHQX WHAX t WHDX Static RAMs Aug 11, 2010 LDS-L7C108/9-F L7C108 L7C109 ...

Page 7

... TYP See detail A 0.025 ± 0.003 0.050 TYP 7 L7C108 L7C109 PRELIMINARY INFORMATION 128K x 8 Static RAM 0.070 ± 0.007 0.082 ± 0.0083 0.055 ± 0.006 0.006 ~ 0.22 TYP 0.003 ~ 0.015 detail A *All measurements in inches 1M Static RAMs Aug 11, 2010 LDS-L7C108/9-F ...

Page 8

... TYP See detail A 0.050 ± 0.005 8 L7C108 L7C109 PRELIMINARY INFORMATION 128K x 8 Static RAM 0.065 ± 0.006 0.020 ± 0.002 0.008R detail A *All measurements in inches 1M Static RAMs Aug 11, 2010 LDS-L7C108/9-F ...

Page 9

... TYP 0.010 REF 0.038 TYP 0.017 ± 0.002 9 PRELIMINARY INFORMATION 128K x 8 Static RAM 0.132 ± 0.0203 0.750 ± 0.007 0.050 BSC 0.005 MIN 0.025 REF 0.075 REF 0.035 ± 0.010 *All measurements in inches 1M Static RAMs Aug 11, 2010 LDS-L7C108/9-F L7C108 L7C109 ...

Page 10

... L7C109 PRELIMINARY INFORMATION 128K x 8 Static RAM 0.05 ± 0.0775 0.100 ± 0.05 TYP 0.018 ± 0.002 0.050 ± 0.002 TYP 0.317 ± 0.011 0.170 ± 0.005 Lead Location Guage Plane Seating Plane Base Plane *All measurements in inches 1M Static RAMs Aug 11, 2010 LDS-L7C108/9-F ...

Page 11

... LOGIC Part # L7C108DMB45 5962-8959827MZA L7C108DMB35 5962-8959828MZA L7C108DMB25 5962-8959829MZA L7C108DMB20 5962-8959839MZA L7C108DMB15 5962-8959844MZA L7C108YMB45 5962-8959827M7A L7C108YMB35 5962-8959828M7A L7C108YMB25 5962-8959829M7A L7C108YMB20 5962-8959839M7A L7C108YMB15 5962-8959844M7A L7C108YMB45 5962-8959827MYA L7C108YMB35 5962-8959828MYA L7C108YMB25 5962-8959829MYA L7C108YMB20 5962-8959839MYA L7C108YMB15 5962-8959844MYA 11 L7C108 L7C109 SMD Part # 1M Static RAMs Aug 11, 2010 LDS-L7C108/9-F ...

Page 12

... LOGIC Devices Incorporated www.logicdevices.com PRELIMINARY INFORMATION 128K x 8 Static RAM LOGIC Part # L7C108YMB45L 5962-8959810M7A L7C108YMB35L 5962-8959811M7A L7C108YMB25L 5962-8959812M7A L7C108YMB20L 5962-8959840M7A L7C108YMB15L 5962-8959848M7A L7C108YAMB45L 5962-8959810MYA L7C108YMB35L 5962-8959811MYA L7C108YMB25L 5962-8959812MYA L7C108YMB20L 5962-8959840MYA L7C108YMB15L 5962-8959848MYA 12 L7C108 L7C109 SMD Part # 1M Static RAMs Aug 11, 2010 LDS-L7C108/9-F ...

Page 13

... I = Industrial Temperature, -40ºC to +85ºC COMPLIANCE MIL-STD-883 Compliant SPEED GRADE: [M]: 15/20/25/35/45 [E]: 15/20/25/35/45 [I]: 15/20/25/35/45 LOW POWER OPTION Low Power No Mark Means Standard Power LOGIC Devices Incorporated www.logicdevices.com PRELIMINARY INFORMATION 128K x 8 Static RAM L 7C 108 L7C108 L7C109 1M Static RAMs Aug 11, 2010 LDS-L7C108/9-F ...

Page 14

... Figure 1a OUTPUT 30 pF INCLUDING JIG AND SCOPE Figure 1b OUTPUT , INCLUDING 5 pF JIG AND , and 2 SCOPE CC1 Figure 2 +3.0 V 90% 10% GND < Static RAMs Aug 11, 2010 LDS-L7C108/9-F L7C108 L7C109 CC 480 255 480 255 90% 10% <3 ns ...

Page 15

... Removed all 108 KA quad LCC and K dual LCC package variants from SMD cross reference table. Updated order information chart to reflect current package availabilities. Changed ICC2 conditions to match ICC3 conditions. Changed operating current to be calculated during the READ cycle. 15 L7C108 L7C109 PRELIMINARY INFORMATION 128K x 8 Static RAM 1M Static RAMs Aug 11, 2010 LDS-L7C108/9-F ...

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