YMF744B ETC [List of Unclassifed Manufacturers], YMF744B Datasheet - Page 23

• Manufacturer Part Number: YMF744B
• Description: DS-1S
• Manufacturer: ETC [List of Unclassifed Manufacturers]

YMF744B
4A-4Bh: DS-1S Power Control 1
b0................DMC: Disable Master Clock Oscillation
b2................DPLL: Disable PLL Clock Oscillation
b6................JSR: Joystick Reset
b8................PR0: AC’97 Power Down Control 0
b9................PR1: AC’97 Power Down Control 1
b10..............PR2: AC’97 Power Down Control 2
b11..............PR3: AC’97 Power Down Control 3
PR7
Setting this bit to “1” disables the oscillation of the Master Clock (24.576 MHz).
Setting this bit to “1” disables the oscillation of PLL.
This bit controls reset of the flip-flop circuit following the analog comparator stage on the joystick port.
The Initial value is set to “0” immediately after power on reset or hardware reset.
This bit controls the power state of the ADC and Input Mux in the Primary AC’97.
This bit controls the power state of the DAC in the Primary AC’97.
This bit controls the power state of the Analog Mixer (Vref still on) in the Primary AC’97. This power
state retains the Reference Voltage of the AC’97.
This bit controls the power state of the Analog Mixer (Vref off) in the Primary AC’97. This power
state removes Reference Voltage of the AC’97.
b15
“0”: Normal
“1”: Disable
“0”: Normal
“1”: Disable
“0”: Normal
“1”: Resets the flip-flop circuit following the analog comparator stage on the joystick port
“0”: Normal
“1”: Power down
“0”: Normal
“1”: Power down
“0”: Normal
“1”: Power down
“0”: Normal
“1”: Power down
Read / Write
Default: 0000h
Access Bus Width: 8, 16, 32-bit
PR6
b14
PR5
b13
PR4
b12
(default)
(default)
(default)
(default)
(default)
(default)
(default)
PR3
b11
PR2
b10
PR1
b9
-23-
PR0
b8
b7
-
JSR
b6
b5
-
b4
-
b3
-
February 3, 1999
DPLL
b2
b1
-
DMC
b0