IC62LV256 ICSI [Integrated Circuit Solution Inc], IC62LV256 Datasheet - Page 7

• Manufacturer Part Number: IC62LV256
• Description: 32K x 8 Low Power SRAM with 3.3V
• Manufacturer: ICSI [Integrated Circuit Solution Inc]

IC62LV256
Integrated Circuit Solution Inc.
ALSR007-0A 10/5/2001
WRITE CYCLE SWITCHING CHARACTERISTICS
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
2. Tested with the load in Figure 1b. Transition is measured
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
4. Tested with OE HIGH.
AC WAVEFORMS
WRITE CYCLE NO. 1 (WE
Symbol
t
t
t
t
t
t
t
t
and output loading specified in Figure 1a.
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
WC
SCE
AW
HA
SA
PWE
SD
HD
(4)
ADDRESS
Write Cycle Time
CE to Write End
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
Parameter
D
OUT
WE
D
CE
IN
WE
WE
WE
WE Controlled)
t
DATA UNDEFINED
SA
Min.
45
35
25
25
20
0
0
0
(1,2)
-45 ns
t
AW
t
HZWE
Max.
—
—
—
—
—
—
—
—
±
t
SCE
500 mV from steady-state voltage. Not 100% tested.
t
WC
t
PWE
(1,2,3)
HIGH-Z
Min.
70
60
60
55
30
0
0
0
t
(Over Operating Range)
SD
-70 ns
DATA-IN VALID
Max.
—
—
—
—
—
—
—
—
t
HA
t
t
LZWE
HD
Min.
100
80
80
60
35
0
0
0
-100 ns
Max.
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
7