AX88850 ASIX [ASIX Electronics Corporation], AX88850 Datasheet - Page 21

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AX88850

Manufacturer Part Number
AX88850
Description
100BASE-TX/FX Repeater Controller
Manufacturer
ASIX [ASIX Electronics Corporation]
Datasheet
3.6 Expansion Logic(Cascade Interface)
The expansion logic is used to stack numerous repeaters. The expansion logic can be divided into two types:
3.7 Management Logic
AX88850 provides the required management information associated with a packet for management chip which
statistics processed on a per packet basis. Transmit ready signal TX_RDY is used as a framing signal for management
data MD. Then management chip uses this data to determine the source of the current packet. MD data is synchronized
to the rising edge of IRD_CK. When collision occur, MD will be tri-state and becomes invalid.
Notes:
Expansion Logic with Buffer (maximum mode
In this mode, use /IR_ACTO[7:0] and /IR_ACTI[7:0] to cascade repeaters. Buffers are used both in
/IR_ACTO[7:0] and /IR_ACTI[7:0]. This mode is supposed to cascade repeaters on difference boards via cables.
There is a configuration bit /IR_ACT_EN to decide cascade signals are judges by /IR_ACTI[7:0](/IR_ACT_EN
= 0) or /IR_ACTO[7:0](/IR_ACT_EN = 1).
Expansion Logic without Buffer (minimum mode)
In this mode, use /IR_ACTO[7:0] to cascade repeaters. Just connect /IR_ACTO[7:0] without using buffer in this
part. This mode is supposed to cascade repeaters on the same board.
In this table:
a.
b.
c.
MD frame format
a.
b.
c.
idle
1
All /IR_ACTO[7:0] will be in open-drain state when repeater chip is idle. These signals are all high via
external pull high resister.
One signal of /IR_ACTO[7:0] is low in data forwarding state corresponding to different RPTR_ID[2:0].
Two signals of /IR_ACTO[7:0] are low in collision state corresponding to different RPTR_ID[2:0].
AX88850
PID[4:0] is the number of the receiving port.
RID_CH indicates change in RID.
PARITY = 1 when sum of 1‘s among PID[4:0] and RID_CH is even
PARITY = xnor (PID[4],PID[3],PID[2],PID[1],PID[0],RID_CH)
RPTR_ID<2:0>
start bit
0
0
1
2
3
4
5
6
7
PID[0]
data0
PID[1]
data1
Idle
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
/IR_ACTO<7:0>
PID[2]
data2
21
PID[3]
data3
Active
FDh
FBh
DFh
BFh
FEh
EFh
F7h
7Fh
ASIX ELECTRONICS CORPORATION
PID[4]
data4
RID_CH
PRELIMINARY
data5
Collision
FBh
FCh
CFh
F9h
F3h
E7h
9Fh
3Fh
PARITY
data6

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