CH7005C-V ETC [List of Unclassifed Manufacturers], CH7005C-V Datasheet - Page 7
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CH7005C-V
Manufacturer Part Number
CH7005C-V
Description
Digital PC to TV Encoder with Macrovision
Manufacturer
ETC [List of Unclassifed Manufacturers]
Datasheet
1.CH7005C-V.pdf
(49 pages)
CHRONTEL
CH7005C
The clock and timing signals used to latch and process the incoming pixel data is dependent upon the clock mode.
The CH7005 can operate in either master (the CH7004 generates a pixel frequency which is either returned as a
phase-aligned pixel clock or used directly to latch data), or slave mode (the graphics chip generates the pixel clock).
The pixel clock frequency will change depending upon the active image size (e.g., 640x480 or 800x600), the desired
output format (NTSC or PAL), and the amount of scaling desired. The pixel clock may be requested to be 1X, 2X,
or 3X the pixel data rate (subject to a 100MHz frequency limitation). In the case of a 1X pixel clock the CH7005
will automatically use both clock edges, if a multiplexed data format is selected.
Sync Signals: Horizontal and vertical sync signals will normally be supplied by the VGA controller, but may be
selected to be generated by the CH7005. In the case of CCIR656 style input (IDF = 1 or 9), embedded sync may
also be used. (In each case, the period of the horizontal sync should be equal to the duration of the pixel clock, time
the first value of the (Total Pixels/line x Total Lines/Frame) column of Table 16 on page 31 (Display Mode
Register 00H description). The leading edge of the horizontal sync is used to determine the start of each line. The
Vertical sync signal must be able to be set to the second value in the (Total Pixels/Line x Total Lines/Frame) column
of Table 16 on page 31.)
Master Clock Mode: The CH7005 generates a clock signal (output at the P-OUT pin) which will be used by the
VGA controller as a frequency reference. The VGA controller will then generate a clock signal which will be input
via the XCLK input. This incoming signal will be used to latch (and de-multiplex, if required) incoming data. The
XCLK input clock rate must match the input data rate, and the P-OUT clock can be requested to be 1X, 2X or 3X
the pixel data rate. As an alternative, the P-OUT clock signal can also be used as the input clock signal (connected
directly to the XCLK input) to latch the incoming data. If this mode is used, the incoming data must meet setup and
hold times with respect to the XCLK input (with the only internal adjustment being XCLK polarity).
Slave Clock Mode: The VGA controller will generate a clock which will be input to the XCLK pin (no clock
signal will be output on the P-OUT pin). This signal must match the input data rate, must occur at 1X, 2X or 3X the
pixel data rate, and will be used to latch (and de-multiplex if required) incoming data. Also, the graphics IC
transmits back to the TV encoder the horizontal and vertical timing signals, and pixel data, each of which must meet
the specified setup and hold times with respect to the pixel clock.
Pixel Data: Active pixel data will be expected after a programmable number pixels times the multiplex rate after
the leading edge of Horizontal Sync. In other words, specifying the horizontal back porch value (as a pixel count),
plus horizontal sync width, will determine when the chip will begin to sample pixels.
Non-multiplexed Mode
In the 15/16-bit mode shown in Figure 4, the pixel data bus represents a 15/16-bit non-multiplexed data stream,
which contains either RGB or YCrCb formatted data. When operating in RGB mode, each 15/16-bit Pn value will
contain a complete pixel encoded in either 5-6-5 or 5-5-5 format. When operating in YCrCb mode, each 16-bit Pn
word will contain an 8-bit Y (luminance) value on the upper 8 bits, and an 8-bit C (color difference) value on the
lower 8 bits. The color difference will be transmitted at half the data rate of the luminance data, with the sequence-
being set as Cb followed by Cr. The Cb and Cr data will be cosited with the Y value transmitted with the Cb value,
with the data sequence described in Table 3. The first active pixel is SAV pixels after the leading edge of horizon-
tal sync, where SAV is a bus-controlled register.
201-0000-025 Rev 2.1, 8/2/99
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