CH7012 ETC [List of Unclassifed Manufacturers], CH7012 Datasheet

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... SC SD 201-0000-042 Rev. 1.1, 9/29/2000 General Description The CH7012 is a display controller device which accepts a digital graphics input signal, and encodes and transmits data output (analog composite, s- video or RGB). The device accepts data over one 12-bit wide variable voltage data port which supports five different data formats including RGB and YCrCb ...

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... DGND GPIO[ GPIO[ DGND 11 12 DVDD 13 RESET AGND 16 2 Chrontel CH7012 Figure 2: 64-Pin LQFP CH7012A SYNC 47 BCO 46 P-OUT 45 DVDDV 44 AVDD FIN 41 AGND 40 GND 39 CVBS / CVBS 35 ISET 34 GND ...

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... This pin functions as the clock pin of the and uses the DVDD supply. ISET Current Set Resistor Input This pin sets the DAC current. A 140 ohm resistor should be connected between this pin and GND (DAC ground) using short and wide traces. CH7012A interface, serial port 3 ...

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... CMOS clock is attached to XI/FIN, XO should be left open. P-OUT Pixel Clock Output When the CH7012 is operating as a VGA to TV encoder in master clock mode, this pin provides a pixel clock signal to the VGA controller which is used as a reference frequency. The output is selectable between the pixel clock frequency ...

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... External Clock Inputs These inputs form a differential clock signal input to the XCLK* CH7012 for use with the and D[11:0] data. If differential clocks are not available, the XCLK* input should be connected to VREF. The output clocks from this pad cell are able to have their polarities reversed under the control of the MCP bit ...

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... Data will be 2X multiplexed, and the XCLK clock signal can times the pixel rate. The input data will be encoded into the selected video standard, and output from the video DAC’s. The modes supported for TV output are shown in the table below, and a block diagram of the CH7012 is shown on the following page. ...

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... Latch, Demux H,V H Latch VREF 201-0000-042 Rev. 1.1, 9/29/2000 TV-DLL Scal Scan Conv Encode 24 Flicker Filt Figure 3: TV Output Modes CH7012A C/H SYNC ISET CVBS (DAC3) Four Y (DAC 1) 10- (DAC 2) DAC's CVBS (DAC0) 24 GPIO[1:0] Seri Port SC Control ...

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... For the multiplexed data, clock at 1X pixel rate the data applied to the CH7012 is latched with both edges of the clock (also referred to as dual-edge transfer mode). For the multiplexed data, clock at 2X pixel rate the data applied to the CH7012 is latched with one edge of the clock. The polarity of the pixel clock can be reversed under control ...

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... The 12 data inputs support 5 different multiplexed data formats, each of which can be used with a 1X clock latching data on both clock edges clock latching data with a single edge. The data received by the CH7012 can be used to drive the VGA to TV encoder or directly drive the DAC’s. The multiplexed input data formats are (IDF[2:0]): ...

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... Data) P[7:0] (Blue Data) Figure 5: Multiplexed Input Data Formats (IDF = SAV P0a P0b P0b[11:4] P0b[3:0], P0a[11:8] P0b[11:7], P0b[3:1] P0b[6:4], P0a[11:9], P0b[0], P0a[3] P0a[8:4], P0a[2:0] CH7012A P1a P1b P2a P2b P1b[11:4] P2b[11:4] P2b[3:0], P1b[3:0], P1a[11:8] P2a[11:8] P0a[7:0] P1a[7:0] P2a[7:0] P2b[11:7] P1b[11:7], P1b[3:1] ...

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... CRA (internal signal) P[23:16] (Y Data) P[15:8] (CrCb Data) P[7:0] (ignored) Multiplexed Input Data Formats (IDF = Figure 6: 201-0000-042 Rev. 1.1, 9/29/2000 SAV P0a P0b P0b[6:4], P0a[11:9] P0b[5:4], P0a[11:9] CH7012A P1a P1b P2a P2b P0b[11:7] P1b[11:7] P2b[11:7] P2b[6:4], P1b[6:4], P1a[11:9] P2a[11:9] P0a[8:4] P1a[8:4] P2a[8:4] P0b[10:6] P1b[10:6] ...

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... RGB 5-6-5 P0b P1a P1b P0a R0[7] G1[4] R1[7] G0[5] R0[6] G1[3] R1[6] G0[4] R0[5] G1[2] R1[5] G0[3] R0[4] B1[7] R1[4] B0[7] R0[3] B1[6] R1[3] B0[6] G0[7] B1[5] G1[7] B0[5] G0[6] B1[4] G1[6] B0[4] G0[5] B1[3] G1[5] B0[3] 4 YCrCb 8-bit P0b P1a P1b P2a Y0[7] Cr0[7] Y1[7] Cb2[7] Y0[6] Cr0[6] Y1[6] Cb2[6] Y0[5] Cr0[5] Y1[5] Cb2[5] Y0[4] Cr0[4] Y1[4] Cb2[4] Y0[3] Cr0[3] Y1[3] Cb2[3] Y0[2] Cr0[2] Y1[2] Cb2[2] Y0[1] Cr0[1] Y1[1] Cb2[1] Y0[0] Cr0[0] Y1[0] Cb2[0] CH7012A 1 12-bit RGB (12-12) P0b P1a P1b R0[7] G1[4] R1[7] R0[6] G1[3] R1[6] R0[5] G1[2] R1[5] R0[4] B1[7] R1[4] R0[3] B1[6] R1[3] G0[7] B1[5] G1[7] G0[6] B1[4] G1[6] G0[5] B1[3] G1[5] R0[2] G1[0] R1[2] R0[1] B1[2] R1[1] R0[0] B1[1] R1[0] G0[1] B1[0] G1[1] 3 RGB 5-5-5 P0b P1a P1b X G1[5] X R0[7] G1[4] R1[7] R0[6] G1[3] R1[6] R0[5] B1[7] R1[5] R0[4] B1[6] R1[4] R0[3] B1[5] R1[3] G0[7] B1[4] G1[7] G0[6] B1[3] G1[6] P2b P3a P3b Y2[7] ...

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... Bits S[7] and S[3..0] are ignored. 201-0000-042 Rev. 1.1, 9/29/2000 4 YCrCb 8-bit P0b P1a P1b P2a 00 00 S[7] Cb2[ S[6] Cb2[ S[5] Cb2[ S[4] Cb2[ S[3] Cb2[ S[2] Cb2[ S[1] Cb2[ S[0] Cb2[0] CH7012A P2b P3a P3b Y2[7] Cr2[7] Y3[7] Y2[6] Cr2[6] Y3[6] Y2[5] Cr2[5] Y3[5] Y2[4] Cr2[4] Y3[4] Y2[3] Cr2[3] Y3[3] Y2[2] Cr2[2] Y3[2] Y2[1] Cr2[1] Y3[1] Y2[0] Cr2[0] Y3[0] 13 ...

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... Black times (F and H) vary with position controls Figure 7: NTSC / PAL Composite Output 14 Level (mV) NTSC PAL 287 300 0 0 287 300 287 300 287 300 340 300 340 300 340 300 CH7012A Duration (uS) NTSC PAL 1.49 - 1.51 1.48 - 1.51 4.69 - 4.72 4.69 - 4.71 0.59 - 0.61 0.88 - 0.92 2.50 - 2.53 2.24 - 2.26 1.55 - 1.61 2.62 - 2.71 0.00 - 7.50 0.00 - 8.67 37.66 - 52.67 34.68 - 52.01 0.00 - 7.50 0.00 - 8.67 201-0000-042 Rev. 1.1, 9/29/2000 ...

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... Interlaced NTSC Video Timing CH7012A 271 272 273 274 275 268 268 269 269 270 270 ...

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... ANALOG FIELD 4 FIELD 4 312 313 314 315 316 317 312 313 314 315 316 317 4 3 ° ° ° ° ° ° CH7012A 318 319 320 321 322 323 318 319 320 321 322 323 6 6 ...

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... Green 18.98 Magenta 15.62 Red 13.49 Blue 10.14 Blank/ Black 8.00 Sync 0.00 Figure 11: PAL Y (Luminance) Video Output Waveform (DACG = 1) 201-0000-042 Rev. 1.1, 9/29/2000 Color bars: V 1.000 0.925 0.801 0.726 0.608 0.533 0.415 0.340 0.287 0.000 Color bars: V 1.003 0.923 0.792 0.712 0.586 0.506 0.380 0.300 0.000 CH7012A 17 ...

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... Green/Magenta 26.68 1.000 Yellow/Blue 23.93 0.897 Peak Burst 19.21 0.720 Blank 15.24 0.572 Peak Burst 11.28 0.423 Yellow/Blue 6.56 0.246 Green/Magenta 3.81 0.143 Cyan/Red 2.97 0.111 Figure 13: PAL C (Chrominance) Video Output Waveform (DACG = 1) 18 Color bars: (9 cycles) Color bars: 4.433619 MHz Color Burst (10 cycles) CH7012A 201-0000-042 Rev. 1.1, 9/29/2000 ...

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... Color/Level V Peak Chrome 33.31 1.249 White 26.75 1.003 Peak Burst 11.97 0.449 Blank/Black 8.00 0.300 Peak Burst 4.04 0.151 Sync 0.00 0.000 Figure 15: Composite PAL Video Output Waveform (DACG = 1) 201-0000-042 Rev. 1.1, 9/29/2000 Color bars: 3.579545 MHz Color Burst (9 cycles) Color bars: 4.433619 MHz Color Burst (10 cycles) CH7012A 19 ...

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... CHRONTEL Register Control The CH7012 is controlled via an serial port control. The serial port bus uses only the SC clock to latch data into registers, and does not use any internally generated clocks so that the device can be written to in all power down modes. The device retains all register states. ...

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... Calculated sub-carrier control (hysteresis, CIV[25:0] Calculated sub-carrier increment value read out CIVPN Select PAL-N when in a CIV mode MEM[2:0] Memory sense amp reference adjust VBID Vertical blanking interval defeat PLLCPI TV-Out PLL charge pump current control PLLCAP TV-Out capacitor control 201-0000-042 Rev. 1.1, 9/29/2000 CH7012A 21 ...

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... CHRONTEL Registers Read/Write Regarding the CH7012 registers read/write operation, please see applications note AN-42 for details. Non-Macrovision Control Registers Description Table 9: Serial Port Register Map w/o Macrovision Register Bit 7 Bit 6 00h IR2 IR1 01h VOF0 02h VBID CFRB 03h 04h SAV7 SAV6 05h ...

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... R/W DEFAULT: 0 Register DM provides programmable control of the CH7012 VGA to TV display mode, including input resolution (IR[2:0]), video output standard (VOS[1:0]), and scaling ratio (SR[2:0]). The mode of operation is determined according to Table 10 below. For entries in which the output standard is shown as PAL, PAL-B,D,G,H,I,N,N through proper selection of the chroma sub-carrier. For entries in which the output standard is shown as NTSC, NTSC- M,J and PAL-M can be supported through proper selection of VOS[1:0] and chroma sub-carrier ...

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... NTSC PAL CFF1 CFF0 YFFT1 R/W R/W R CH7012A 11 NTSC-J Symbol: FF Address: 01h Bits YFFT0 YFFNT1 YFFNT0 R/W R/W R 201-0000-042 Rev. 1.1, 9/29/2000 0 1 ...

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... CH7012A Symbol: VBW Address: 02h Bits YSV0 YCV1 YCV0 R/W R 3.540 5.880 4.430 7.350 3 ...

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... TYPE: DEFAULT: Bits 2-0 of register TE control the text enhancement circuitry within the CH7012. A value of ‘000’ minimizes the enhancement feature, while a value of ‘111’ maximizes the enhancement. Bits 5-3 of register TE contain the MSB values for the start of active video, horizontal position and vertical position controls ...

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... Rev. 1.1, 9/29/2000 SAV5 SAV4 SAV3 R/W R/W R HP5 HP4 HP3 R/W R/W R VP5 VP4 VP3 R/W R/W R CH7012A Symbol: SAV Address: 04h Bits SAV2 SAV1 SAV0 R/W R Symbol: HP Address: 05h Bits HP2 HP1 R/W R Symbol: VP Address: ...

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... BIT: 7 SYMBOL: TYPE: DEFAULT: Bits 2-0 of register CE control contrast enhancement feature of the CH7012, according to the figure below. A setting of ‘0’ results in reduced contrast, a setting of ‘1’ leaves the image contrast unchanged, and values beyond ‘1’ result in increased contrast. 512 444 376 308 < ...

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... Rev. 1.1, 9/29/2000 IBI N9 R/W R/W R Mode PLLCAP Value CH7012A Symbol: TPC Address: 09h Bits PLLCPI PLLCAP R ...

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... Register PLLM controls the division factor applied to the 14.31818MHz frequency reference clock before it is input to the TV PLL phase detector when the CH7012 is operating in master clock mode. The entire bit field, M[8:0], is comprised of this register M[7:0] plus the MSB value contained in the TV PLL Control register, bit M8. In slave clock mode, an external pixel clock is used instead of the 14 ...

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... FSCI[7:0] When the CH7012 is used in the master clock mode, the tables below should be used to set the FSCI registers. When using these values, the CIVEN bit in register 10h should be set to ‘0’, and the CFRB bit in register 02h should be set to ‘1’. ...

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... Dot Crawl” 651,209,077 520,967,262 486,236,111 379,871,962 547,015,625 434,139,385 651,209,077 520,967,262 434,139,385 558,179,209 455,846,354 390,725,446 521,519,134 427,355,957 366,305,106 502,361,288 439,566,127 390,725,446 569,807,942 CIV25 CIV24 CIVC1 R/W R/W R CH7012A Symbol: CIVC Address: 10h Bits CIVC0 PALN CIVEN R/W R 201-0000-042 Rev. 1.1, 9/29/2000 0 R/W 1 ...

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... Bit 2 of register CM controls the phase of the XCLK clock input to the CH7012. A value of ‘1’ inverts the XCLK signal at the input of the device. This control is used to select which edge of the XCLK signal to use for latching input data ...

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... R/W R/W R R/W R/W R SYO VSP HSP R/W R/W R CH7012A Symbol: IC Address: 1Dh Bits XCMD1 XCMD0 R/W R Symbol: GPIO Address: 1Eh Bits POUTE POUTP R/W R ...

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... Bit 5 of register IDF controls the sync direction. A value of ‘0’ defines sync to be input to the CH7012, and a value of ‘1’ defines sync to be output from the CH7012. The CH7012 can only output sync signals when operating as a VGA to TV encoder ...

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... SHF0 BCOEN BCOP R/W R/W R BCO[2:0] Buffered Clock Output 100 (for test use only) 101 (for test use only) 110 VGA Vertical Sync 111 TV Vertical Sync CH7012A Symbol: DC Address: 21h Bits DACG1 DACG0 DACBP R/W R Symbol: BCO Address: 22h ...

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... Rev. 1.1, 9/29/2000 ResetIB ResetDB R/W R/W 1 serial port reset signal. A value of ‘0’ holds the serial port registers in normal mode. The CH7012A Symbol: TSTP Address: 48h Bits RSA TSTP1 TSTP0 R/W ...

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... Register VID is a read only register containing the version ID number of the CH7012. Device ID Register BIT: 7 SYMBOL: DID7 DID6 TYPE: R DEFAULT: 0 Register DID is a read only register containing the device ID number of the CH7012 DACPD3 DACPD2 DACPD1 DACPD0 R/W R/W R Operational When & ...

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... Video level error 4 DAC’s Enabled I VDD I 3 DAC’s Enabled VDD I AVDD I DVDD DVDDV (1.8V) curent (15pF load) 201-0000-042 Rev. 1.1, 9/29/2000 Min - 0.5 1 GND - 0 Min 3.1 3.1 3.1 1 Min 10 CH7012A Typ Max Units 5.0 V VDD + 0.5 V Indefinite Sec 85 C 150 C 150 C 220 C 5V can 0. Typ Max Units 3.3 3.6 V 3.3 3 ...

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... DATA V - refers to serial port pin output refers to pixel data output Time - Grapics. P-OUT 40 Test Condition Min IOL = 2.0 mA 2.7 GND-0.5 Vref-0.25 GND-0.5 IOL = - 400 A DVDDV-0.2 IOL = 3.2 mA CH7012A Typ Max Unit 0.4 V DVDD + 0.5 V 1.4 V DVDD+0.5 V Vref+0. 0.2 V 201-0000-042 Rev. 1.1, 9/29/2000 ...

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... CHRONTEL Mechanical Package Information 201-0000-042 Rev. 1.1, 9/29/2000 CH7012A 41 ...

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... CHRONTEL Part number CH7012A-T 1998 Chrontel, Inc. All Rights Reserved. Chrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WIT HOUT THE SPECIFIC WRITTEN CONSENT OF Chrontel. Life support systems are those intended to support or sustain life and whose failure to p erform when used as directed can reasonably expect to result in personal injury or death ...