QL3012-0PL84M ETC1 [List of Unclassifed Manufacturers], QL3012-0PL84M Datasheet
QL3012-0PL84M
Related parts for QL3012-0PL84M
QL3012-0PL84M Summary of contents
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... Interfaces with both 3.3 volt and 5.0 volt devices PCI compliant with 3.3V and 5.0V buses for -1/-2 speed grades Full JTAG boundary scan Registered I/O cells with individually controlled clocks and output enables Device QL3012 QL3025 QL3040 QL3060 M = Military Temperature (-55 to +125 degrees C) Rev B Features Total of 180 I/O pins 308 bidirectional input/output pins, PCI-compliant for 5 ...
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Military Plastic pASIC 3 Family P S RODUCT UMMARY Product Summary The pASIC 3 FPGA family features up to 60,000 usable PLD gates. pASIC 3 FPGAs are fabricated on a 0.35mm four-layer metal process using Quick- Logic’s patented ViaLink technology ...
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Military Plastic pASIC 3 Family P D INOUT IAGRAM Pinout Diagram 208-Pin PQFP Pin #1 QL3060-1PQ208M Pin #53 208-P PQFP IN pASIC Pin #157 Pin #105 8-25 ...
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Military Plastic pASIC 3 Family PQFP 208-P 208 Function PQFP 208 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O NC I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 VCC 11 I/O 12 GND 13 I/O ...
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Military Plastic pASIC 3 Family ABSOLUTE MAXIMUM RATINGS VCC Voltage ...........................-0.5 to 4.6V VCCIO Voltage .......................-0.5 to 7.0V Input Voltage.............. -0.5 to VCCIO+0.5V .................. ±200 mA Latch-up Immunity OPERATING RANGE Symbol VCC Supply Voltage VCCIO I/O Input Tolerance Voltage TA ...
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... These limits are derived from a representative selection of the slowest paths through the pASIC 3 logic cell including typical net delays. Worst case delay values for specific paths should be determined from timing analysis of your particular design. 8-28 28 QL3012 Logic Cells Propagation Delays (ns) Fanout [ ...
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... Military Plastic pASIC 3 Family QL3012 Clock Cells Symbol Parameter tACK Array Clock Delay tGCKP Global Clock Pin Delay tGCKB Global Clock Buffer Delay Symbol Parameter tI/O Input Delay (bidirectional pad) tISU Input Register Set-Up Time tIH Input Register Hold Time tlOCLK Input Register Clock To Q ...
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Military Plastic pASIC 3 Family QL3025 AC CHARACTERISTICS at VCC = 3.3V (To calculate delays, multiply the appropriate K factor in the "Operating Range" section by the following numbers.) Symbol Parameter tPD Combinatorial Delay [6] tSU Setup ...
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Military Plastic pASIC 3 Family QL3025 Clock Cells Symbol Parameter tACK Array Clock Delay tGCKP Global Clock Pin Delay tGCKB Global Clock Buffer Delay Symbol Parameter tI/O Input Delay (bidirectional pad) tISU Input Register Set-Up Time tIH Input Register Hold ...
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Military Plastic pASIC 3 Family QL3040 AC CHARACTERISTICS at VCC = 3.3V (To calculate delays, multiply the appropriate K factor in the "Operating Range" section by the following numbers.) Symbol Parameter tPD Combinatorial Delay [6] tSU Setup ...
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Military Plastic pASIC 3 Family QL3040 Clock Cells Symbol Parameter tACK Array Clock Delay tGCKP Global Clock Pin Delay tGCKB Global Clock Buffer Delay Symbol Parameter tI/O Input Delay (bidirectional pad) tISU Input Register Set-Up Time tIH Input Register Hold ...
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Military Plastic pASIC 3 Family QL3060 AC CHARACTERISTICS at VCC = 3.3V (To calculate delays, multiply the appropriate K factor in the "Operating Range" section by the following numbers.) Symbol Parameter tPD Combinatorial Delay [6] tSU Setup ...
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Military Plastic pASIC 3 Family QL3060 Clock Cells Symbol Parameter tACK Array Clock Delay tGCKP Global Clock Pin Delay tGCKB Global Clock Buffer Delay Symbol Parameter tI/O Input Delay (bidirectional pad) tISU Input Register Set-Up Time tIH Input Register Hold ...
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Military Plastic pASIC 3 Family Pin Function TDI Test Data In for JTAG TRSTB Active low Reset for JTAG TMS Test Mode Select for JTAG TCK Test Clock for JTAG TDO Test data out for JTAG STM Special Test Mode ...