QL3012-0PL84M ETC1 [List of Unclassifed Manufacturers], QL3012-0PL84M Datasheet - Page 11

• Manufacturer Part Number: QL3012-0PL84M
• Description: 60,000 Usable PLD Gate pASIC3 FPGA Combining High Performance and High Density
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

Notes:
[7] The array distributed networks consist of 72 half columns and the global distributed networks consist of
[8] The following loads are used for tPXZ:
Symbol
tOUTLH
tOUTHL
tPZH
tPZL
tPHZ
tPLZ
Symbol
tI/O
tISU
tIH
tlOCLK
tlORST
tlESU
tlEH
Symbol
tACK
tGCKP
tGCKB
76 half columns, each driven by an independent buffer. The number of half columns used does not
affect clock buffer delay. The array clock has up to 14 loads per half column. The global clock has up
to 16 loads per half column.
Output Delay Low to High
Output Delay High to Low
Output Delay Tri-state to High
Output Delay Tri-state to Low
Output Delay High to Tri-State [8]
Output Delay Low to Tri-State [8]
Input Delay (bidirectional pad)
Input Register Set-Up Time
Input Register Hold Time
Input Register Clock To Q
Input Register Reset Delay
Input Register clock Enable Set-Up Time
Input Register Clock Enable Hold Time
Array Clock Delay
Global Clock Pin Delay
Global Clock Buffer Delay
Parameter
Military Plastic pASIC 3 Family
1KΩ
Parameter
Parameter
QL3040 Clock Cells
1.2
0.7
0.8
tPHZ
1
I/O Cells
5 pF
1.2
0.7
0.8
2
0.7
0.9
1.3
3
Loads per Half Column [7]
2.1
2.2
1.2
1.6
2.0
1.2
1.3
3.1
0.0
0.7
0.6
2.3
0.0
30
Propagation Delays (ns)
1
Output Load Capacitance (pF)
1KΩ
0.7
0.9
1.3
4
Propagation Delays (ns)
Propagation Delays (ns)
1.6
3.1
0.0
1.0
0.9
2.3
0.0
2.5
2.6
1.7
2.0
2
50
1.5
0.7
1.1
8
tPLZ
5 pF
Fanout [5]
1.8
3.1
0.0
1.2
1.1
2.3
0.0
3
3.1
3.2
2.2
2.6
1.6
0.7
1.2
75
10
2.1
3.1
0.0
1.5
1.4
2.3
0.0
4
1.7
0.7
1.3
12
100
3.6
3.7
2.8
3.1
3.1
2.5
2.4
2.3
0.0
3.1
0.0
8
1.8
0.7
1.4
14
150
4.7
4.8
3.9
4.2
3.6
2.3
3.1
0.0
3.0
2.9
0.0
10
1.9
0.7
1.5
16
8-33