EX256-CS100A ACTEL [Actel Corporation], EX256-CS100A Datasheet - Page 15

• Manufacturer Part Number: EX256-CS100A
• Description: eX Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

Explorer II's noninvasive method does not alter timing or
loading effects, thus shortening the debug cycle.
Silicon Explorer II does not require re-layout or
additional MUXes to bring signals out to an external pin,
which is necessary when using programmable logic
devices from other suppliers.
Silicon
(asynchronous) or 66 MHz (synchronous). Silicon Explorer
II attaches to a PC's standard COM port, turning the PC
into a fully functional 18-channel logic analyzer. Silicon
Explorer II allows designers to complete the design
verification
verification time from several hours per cycle to a few
seconds.
The Silicon Explorer II tool uses the boundary scan ports
(TDI, TCK, TMS and TDO) to select the desired nets for
verification. The selected internal nets are assigned to the
PRA/PRB pins for observation.
Table 1-8 • Device Configuration Options for Probe Capability (TRST pin reserved)
Figure 1-13 • Silicon Explorer II Probe Setup
JTAG Mode
Dedicated
Flexible
Dedicated
Flexible
–
Notes:
1. If TRST pin is not reserved, the device behaves according to TRST = HIGH in the table.
2. Avoid using the TDI, TCK, TDO, PRA, and PRB pins as input or bidirectional ports. Since these pins are active during probing, input
3. If no user signal is assigned to these pins, they will behave as unused I/Os in this mode. Unused pins are automatically tristated by
signals will not pass through these pins and may cause contention.
Actel’s Designer software.
Explorer
process
II
TRST
at
samples
HIGH
HIGH
LOW
LOW
–
their
1
Figure 1-13
Connection
data
desks
Serial
Security Fuse Programmed
at
Additional 16 Channels
and
illustrates the
(Logic Analyzer)
Silicon Explorer II
100
reduces
MHz
Yes
No
No
No
No
v4.3
Connection
Connection
interconnection between Silicon Explorer II and the eX
device to perform in-circuit verification.
Design Considerations
The TDI, TCK, TDO, PRA, and PRB pins should not be used
as input or bidirectional ports. Since these pins are active
during probing, critical signals input through these pins
are not available while probing. In addition, the Security
Fuse should not be programmed because doing so
disables the probe circuitry. It is recommended to use a
series 70Ω termination resistor on every probe connector
(TDI, TCK, TMS, TDO, PRA, PRB). The 70Ω series
termination is used to prevent data transmission
corruption during probing and reading back the
checksum.
22 Pin
16 Pin
TMS
TCK
TDO
TDI
PRA
PRB
Probe Circuit Outputs
Probe Circuit Outputs
Probe Circuit Secured
PRA, PRB
User I/O
User I/O
3
3
eX FPGAs
2
Probe Circuit Secured
Probing Unavailable
Probe Circuit Inputs
Probe Circuit Inputs
TDI, TCK, TDO
eX Family FPGAs
User I/O
3
2
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