EX256 Actel Corporation, EX256 Datasheet
EX256
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EX256 Summary of contents
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... Std, – 64, 100 49, 128 datasheet for details on automotive temperature offerings. v4.3 Secure Programming Technology eX128 eX256 6,000 12,000 4,000 8,000 128 256 256 512 256 512 100 132 –F, Std, –P –F, Std, –P ...
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... Note: Package Definitions:TQFP = Thin Quad Flat Pack, CSP = Chip Scale Package Temperature Grade Offerings Device\Package TQFP 64-Pin eX64 eX128 eX256 Notes Commercial I = Industrial A = Automotive Speed Grade and Temperature Grade Matrix Notes Approximately 30% faster than Standard – ...
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Table of Contents eX Family FPGAs General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Family FPGAs General Description The eX family of FPGAs is a low-cost solution for low- power, high-performance designs. The inherent low power attributes of the antifuse technology, coupled with an additional low static power mode, make these devices ideal ...
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Family FPGAs Module Organization C-cell and R-cell logic modules are arranged into horizontal banks called Clusters, each of which contains two C-cells and one R-cell in a C-R-C configuration. Clusters are further organized into modules called SuperClusters for improved ...
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Routing Resources Clusters and SuperClusters can be connected through the use of two innovative local routing resources called FastConnect and DirectConnect, which enable extremely fast and predictable interconnection of modules within Clusters and SuperClusters (Figure architecture also dramatically reduces the ...
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Family FPGAs Clock Resources eX’s high-drive routing structure provides three clock networks. The first clock, called HCLK, is hardwired from the HCLK buffer to the clock select MUX in each R-Cell. HCLK cannot be connected to combinational logic. This ...
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Other Architectural Features Performance The combination of architectural features described above enables eX devices to operate with internal clock frequencies exceeding 350 MHz for very fast execution of complex logic functions. The eX family is an optimal platform upon which ...
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... Table 1-3 illustrates the standby current of eX devices in LP mode. Table 1-3 • Standby Power of eX Devices in LP Mode Typical Conditions, V Product Low Power Standby Current eX64 100 eX128 111 eX256 134 v4.3 Design application note ° 2 CCA CCI ...
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... V, device tested at room temperature. CCA CCI Figure 1-9 • eX Dynamic Power Consumption – Low Frequency show some sample power characteristics of eX devices. 300 250 200 150 100 100 150 Frequency (MHz Frequency (MHz) v4.3 eX Family FPGAs eX64 eX128 eX256 200 eX64 eX128 eX256 50 1-7 ...
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Family FPGAs 180 160 140 120 100 Figure 1-10 • Total Dynamic Power (mW) 12,000 10,000 8,000 6,000 4,000 2,000 0 0 Figure 1-11 • System Power at 5%, 10%, and 15% ...
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Boundary Scan Testing (BST) All eX devices are IEEE 1149.1 compliant. eX devices offer superior diagnostic and testing capabilities by providing Boundary Scan Testing (BST) and probing capabilities. These functions are controlled through the special test pins (TMS, TDI, TCK, ...
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... Programming Device programming is supported through Silicon Sculptor series of programmers. In particular, Silicon Sculptor compact, robust, single-site and multi-site device programmer for the PC. With standalone software, Silicon Sculptor II allows concurrent programming of multiple units from the same PC, ensuring the fastest programming times possible ...
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Explorer II's noninvasive method does not alter timing or loading effects, thus shortening the debug cycle. Silicon Explorer II does not require re-layout or additional MUXes to bring signals out to an external pin, which is necessary when using programmable ...
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Family FPGAs Development Tool Support The eX family of FPGAs is fully supported by both Actel's Libero™ Integrated Design Environment and Designer FPGA Development software. Actel Libero IDE is a design management environment that streamlines the design flow. Libero ...
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... CCA CCI 3.3V Power Supply Range (V ) CCI 5.0V Power Supply Range (V ) CCI Note: *Ambient temperature ( Table 1-11 • Typical eX Standby Current at 25°C Product eX64 eX128 eX256 Limits –0.3 to +6.0 –0.3 to +3.0 –0.5 to +5.75 –0 –65 to +150 Commercial Industrial 0 to +70 –40 to +85 2.3 to 2.7 2.3 to 2.7 3.0 to 3.6 3.0 to 3.6 4.75 to 5.25 4. ...
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Family FPGAs 2.5 V LVCMOS2 Electrical Specifications Symbol Parameter MIN CCI MIN CCI MIN, V ...
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V LVTTL Electrical Specifications Symbol Parameter MIN CCI MIN CCI Input Low Voltage IL ...
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... eqcm C Comb Modules + ( fn) + (0.5 * (q1 * eqi Input Buffers + (0 RCLKA eqcr + (0 fs1)+(C RCLKB eqhv fp) CCI eqo L Output Buffers of input buffers switching clock eX256 0. eqsm * fq2 eqhf ] at ...
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C = Equivalent capacitance eqsm modules C = Equivalent capacitance of input buffers eqi C = Equivalent capacitance of routed array clocks eqcr C = Variable capacitance of dedicated array clock eqhv C = Fixed capacitance of dedicated array clock ...
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Family FPGAs eX Timing Model Input Delays I/O Module t = 0.7 ns INYH Routed t = 1.3 ns RCKH Clock (100% Load) I/O Module t = 1.3 ns INYH Hard-Wired Clock t = 1.1 ns HCKH Note: Values ...
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Output Buffer Delays 50% 50% GND V OH 1.5 V 1.5 V Out DLH t DHL Table 1-13 • Output Buffer Delays AC Test Loads Load 1 (used to measure propagation delay) To the ...
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Family FPGAs Input Buffer Delays PAD INBUF 3V In 1 Out 50% GND t t INY INY Table 1-14 • Input Buffer Delays Cell Timing Characteristics D t SUD CLK Q CLR PRESET Figure ...
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Timing Characteristics Timing characteristics for eX devices fall into three categories: family-dependent, device-dependent, and design-dependent. The input characteristics are common to all eX family members. Internal routing delays are device-dependent. Design dependency means actual delays are not determined until after ...
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Family FPGAs eX Family Timing Characteristics Table 1-17 • eX Family Timing Characteristics (Worst-Case Commercial Conditions, V Parameter Description 1 C-Cell Propagation Delays t Internal Array Module PD 2 Predicted Routing Delays t FO=1 Routing Delay, DirectConnect DC t ...
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Table 1-18 • eX Family Timing Characteristics (Worst-Case Commercial Conditions V Parameter Description Dedicated (Hard-Wired) Array Clock Networks t Input LOW to HIGH HCKH (Pad to R-Cell Input) t Input HIGH to LOW HCKL (Pad to R-Cell Input) t Minimum ...
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Family FPGAs Table 1-19 • eX Family Timing Characteristics (Worst-Case Commercial Conditions V Parameter Description Dedicated (Hard-Wired) Array Clock Networks t Input LOW to HIGH HCKH (Pad to R-Cell Input) t Input HIGH to LOW HCKL (Pad to R-Cell ...
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Table 1-20 • eX Family Timing Characteristics (Worst-Case Commercial Conditions V Parameter Description 2.5 V LVCMOS Output Module Timing t Data-to-Pad LOW to HIGH DLH t Data-to-Pad HIGH to LOW DHL t Data-to-Pad HIGH to LOW—Low Slew DHLS t Enable-to-Pad, ...
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Family FPGAs Pin Description CLKA/B Routed Clock A and B These pins are clock inputs for clock distribution networks. Input levels are compatible with standard TTL or LVTTL specifications. The clock input is buffered prior to clocking the R-cells. ...
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Package Pin Assignments 64-Pin TQFP 64 1 Figure 2-1 • 64-Pin TQFP Note For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html. 64-Pin TQFP v4.3 eX Family FPGAs 2-1 ...
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Family FPGAs 64-Pin TQFP eX64 Pin Number Function 1 GND 2 TDI, I/O 3 I/O 4 TMS 5 GND 6 V CCI 7 I TRST, I GND ...
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TQFP 100 1 Figure 2-2 • 100-Pin TQFP (Top View) Note For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html. 100-Pin TQFP v4.3 eX Family FPGAs 2-3 ...
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... I/O 48 I/O 49 I/O 50 TRST, I/O 51 I/O 52 I CCI CCI I/O 56 I/O 57 I/O 58 I/O 59 I/O 60 I/O 61 I/O 62 I/O 63 I/O 64 I/O 65 I/O 66 I/O 67 I/O 68 PRB, I CCA v4.3 100-Pin TQFP eX64 eX128 eX256 Function Function Function GND GND GND I/O I/O I/O HCLK HCLK HCLK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I CCI CCI CCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDO, I/O TDO, I/O TDO, I/O NC I/O I/O GND GND ...
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... CLKA CLKA 88 CLKB CLKB CCA CCA 91 GND GND 92 PRA, I/O PRA, I/O 93 I/O I/O 94 I/O I/O 95 I/O I/O 96 I/O I/O 97 I/O I/O 98 I/O I/O 99 I/O I/O 100 TCK, I/O TCK, I/O Note: *Please read the LP pin descriptions for restrictions on their use. eX256 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O V CCI I/O I/O I/O I/O CLKA CLKB NC V CCA GND PRA, I/O I/O I/O I/O I/O I/O I/O I/O TCK, I/O v4.3 eX Family FPGAs 2-5 ...
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Family FPGAs 49-Pin CSP A1 Ball Pad Corner Figure 2-3 • 49-Pin CSP (Top View) Note For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html ...
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CSP eX64 Pin Number Function A1 I/O A2 I/O A3 I CCA A6 I/O A7 I/O B1 TCK, I/O B2 I/O B3 I/O B4 PRA, I/O B5 CLKA B6 I/O B7* GND/LP* C1 I/O C2 ...
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Family FPGAs 128-Pin CSP A1 Ball Pad Corner Figure 2-4 • 128-Pin CSP (Top View) Note For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html. ...
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... D12 I/O E1 I/O E2 I/O E3 I/O E4 PRA, I/O E9 CLKB E10 I/O E11* GND/LP* I/O E12 I/O F1 GND F2 I/O F3 I/O F4 TDI, I/O F9 I/O F10 I/O F11 I/O F12 CLKA G1 I/O G2 TRST, I/O I/O G3 I/O G4 I/O G9 I/O G10 v4.3 eX Family FPGAs 128-Pin CSP eX128 eX256 Function Function I/O I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND I/O I/O I/O GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I CCI CCI CCI NC I/O I CCI ...
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... L1 I CCI CCI V L4 CCA I CCA I CCI CCI I/O L9 I/O L10 I/O L11 GND L12 I/O M1 GND M2 I/O M3 I/O M4 I/O M5 I/O M6 I/O M7 I/O M8 I/O M9 I/O M10 PRB, I/O M11 HCLK M12 v4.3 128-Pin CSP eX64 eX128 eX256 Function Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O TDO, I/O TDO, I/O TDO, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC I/O I CCI CCI CCI ...
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CSP A1 Ball Pad Corner Figure 2-5 • 180-Pin CSP Note For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html ...
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... I/O H10 E6 I/O H11 E7 GND H12 E8 I/O H13 E9 GND H14 E10 I/O J1 E11 I/O J2 E12 I/O J3 E13 V J4 CCI E14 I/O J5 v4.3 180-Pin CSP eX256 Pin eX256 Function Number Function I/O J10 I/O I/O J11 V CCI V J12 V CCI CCA I/O J13 I/O GND J14 I/O GND K1 I/O I CCA GND/LP CCA CCI I/O K5 ...
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... M14 I/O N1 I/O N2 GND N3 I/O N4 I/O N5 I/O N6 I CCA N9 I/O N10 I/O N11 I/O N12 I/O N13 I/O N14 I/O P1 I/O P2 I Note: *Please read the LP pin descriptions for restrictions on their use. 180-Pin CSP Pin eX256 Function P10 NC P11 NC P12 GND P13 I/O v4.3 eX Family FPGAs 2-13 ...
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Datasheet Information List of Changes The following table lists critical changes that were made in the current version of the document. Previous version Changes in current version (v4.3) v4.2 The "Ordering Information" was also updated. (June 2004) The "Dedicated Test ...
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... The "TRST, I/O Boundary Scan Reset Pin" section All VSV pins were changed to V 64-Pin TQFP –Pin 36 100-Pin TQFP –Pin 57 49-Pin CSP –Pin D5 128-Pin CSP–Pin H11 and Pin J1 for eX256 180-Pin CSP –Pins J12 and K2 v2.0.1 The "Recommended Operating Conditions" section The " ...
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... A CS128 pin drawing and pin assignment table including eX64, eX128, and eX256 pin functions have been added. A CS180 pin drawing and pin assignment table for eX256 pin functions have been added. pages 27, 31 Advanced v.1 The following table note was added to the eX Timing Characteristics table for clarification: Clock skew improves as the clock network becomes more heavily loaded. " ...
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Family FPGAs Datasheet Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advanced," "Production," and "Datasheet Supplement." The definitions of these categories ...
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... Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. Actel Corporation Actel Europe Ltd. 2061 Stierlin Court Dunlop House, Riverside Way Mountain View, CA Camberley, Surrey GU15 3YL 94043-4655 USA United Kingdom Phone 650.318.4200 Phone +44 (0) 1276 401 450 Fax 650 ...