A54SX08 Actel Corporation, A54SX08 Datasheet
A54SX08
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A54SX08 Summary of contents
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... Deterministic, User-Controllable Timing • Unique In-System Diagnostic and Debug Capability with Silicon Explorer II • Boundary Scan Testing in Compliance with IEEE Standard 1149.1 (JTAG) • Secure Programming Technology Prevents Reverse Engineering and Design Theft A54SX08 A54SX16 8,000 16,000 12,000 24,000 768 1,452 512 924 ...
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... SX Family FPGAs Ordering Information P 2 A54SX16 – Blank = Not PCI Compliant P = PCI Compliant Part Number A54SX08 = 12,000 System Gates A54SX16 = 24,000 System Gates A54SX16P = 24,000 System Gates A54SX32 = 48,000 System Gates Plastic Device Resources PLCC Device 84-Pin A54SX08 69 A54SX16 – A54SX16P – ...
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Table of Contents SX Family FPGAs General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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SX Family FPGAs General Description The Actel SX family of FPGAs features a sea-of-modules architecture that delivers device performance and integration levels not currently achieved by any other FPGA architecture. SX devices greatly simplify design time, enable dramatic reductions in ...
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SX Family FPGAs The R-cell contains a flip-flop featuring asynchronous clear, asynchronous preset, and clock enable (using the S0 and S1 lines) control signals (Figure registers feature programmable clock polarity selectable on a register-by-register basis. This provides additional Routing Tracks ...
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Chip Architecture The SX family chip architecture provides a unique approach to module organization and chip routing that delivers the best register/logic mix for a wide variety of new and emerging applications. Module Organization Actel has arranged all C-cell and ...
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SX Family FPGAs Routing Resources Clusters and SuperClusters can be connected through the use of two innovative local routing resources called FastConnect and DirectConnect, which enable extremely fast and predictable interconnection of modules within clusters and SuperClusters (Figure 1-5 of ...
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... Table 1-1 • Supply Voltages Device V V CCA A54SX08 3.3 V 3.3 V A54SX16 A54SX32 A54SX16-P* 3.3 V 3.3 V 3 ...
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SX Family FPGAs Boundary Scan Testing (BST) All SX devices are IEEE 1149.1 compliant. SX devices offer superior diagnostic and testing capabilities by providing Boundary Scan Testing (BST) and probing capabilities. These functions are controlled through the special test pins ...
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... Operating Conditions Table 1-3 • Absolute Maximum Ratings Symbol Supply Voltage CCR Supply Voltage CCA Supply Voltage (A54SX08, A54SX16, A54SX32) CCI Supply Voltage (A54SX16P) CCI V Input Voltage I V Output Voltage O I I/O Source Sink Current IO T ...
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SX Family FPGAs Table 1-4 • Recommended Operating Conditions Parameter Temperature Range* 3.3 V Power Supply Tolerance 5.0 V Power Supply Tolerance Note: *Ambient temperature ( used for commercial and industrial; case temperature (T A Table 1-5 • ...
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PCI Compliance for the SX Family The SX family supports 3.3 V and 5.0 V PCI and is compliant with the PCI Local Bus Specification Rev. 2.1. Table 1-6 • A54SX16P DC Specifications (5.0 V PCI Operation) Symbol Parameter V ...
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SX Family FPGAs A54SX16P AC Specifications for (PCI Operation) Table 1-7 • A54SX16P AC Specifications for (PCI Operation) Symbol Parameter I Switching Current High OH(AC) (Test Point) I Switching Current High OL(AC) (Test Point) I Low Clamp Current CL slew ...
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Figure 1-9 shows the 5.0 V PCI V/I curve and the minimum and maximum PCI drive characteristics of the A54SX16P device. 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 –0.05 PCI I Mininum OH –0.10 –0.15 –0.20 ...
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SX Family FPGAs A54SX16P DC Specifications (3.3 V PCI Operation) Table 1-8 • A54SX16P DC Specifications (3.3 V PCI Operation) Symbol Parameter V Supply Voltage for Array CCA V Supply Voltage required for Internal Biasing CCR V Supply Voltage for ...
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A54SX16P AC Specifications (3.3 V PCI Operation) Table 1-9 • A54SX16P AC Specifications (3.3 V PCI Operation) Symbol Parameter Condition Switching Current High 0 < V 0.3V I OH(AC) 0.7V (Test Point) V Switching Current High V 0.6V I OL(AC) ...
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SX Family FPGAs Figure 1-10 shows the 3.3 V PCI V/I curve and the minimum and maximum PCI drive characteristics of the A54SX16P device. 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0. –0.05 PCI I Minimum ...
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... V 3.3 V 5.0 V 3.3 V 5.0 V Note: No inputs should be driven (high or low) before completion of power-up. Power-Down Sequencing Table 1-11 • Power-Down Sequencing V V CCA CCR A54SX08, A54SX16, A54SX32 3.3 V 5.0 V A54SX16P 3.3 V 3.3 V 3.3 V 5.0 V 3.3 V 5.0 V Note: No inputs should be driven (high or low) after the beginning of the power-down sequence. V Power-Up Sequence CCI 3 ...
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SX Family FPGAs Evaluating Power in SX Devices A critical element of system reliability is the ability of electronic devices to safely dissipate the heat generated during operation. The thermal characteristics of a circuit depend on the device and package ...
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... Table 1-13 shows capacitance devices. Table 1-13 • Capacitance Values for Devices A54SX08 A54SX16 C (pF) 4.0 4.0 EQM C (pF) 3.4 3.4 EQI C (pF) 4.7 4.7 EQO C (pF) 1.6 1.6 EQCR C 0.615 0.615 EQHV EQHF r (pF) 87 138 1 r (pF) 87 138 2 Table 1-14 • Power Consumption Guidelines Description Logic Modules (m) Inputs Switching (n) Outputs Switching (p) ...
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SX Family FPGAs Step 1: Define Terms Used in Formula Module Number of logic modules switching at f (Used 50%) m Average logic modules switching rate f (MHz) (Guidelines: f/10) m Module capacitance C (pF) EQM Input Buffer Number of ...
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Figure 1-11 shows the characterized power dissipation numbers for the shift register design using frequencies ranging from 1 MHz to 200 MHz. 1200 1000 800 600 400 200 Figure 1-11 • Power Dissipation Junction Temperature (T ) ...
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SX Family FPGAs Table 1-15 • Package Thermal Characteristics Package Type Plastic Leaded Chip Carrier (PLCC) Thin Quad Flat Pack (TQFP) Thin Quad Flat Pack (TQFP) Very Thin Quad Flatpack (VQFP) Plastic Quad Flat Pack (PQFP) without Heat Spreader Plastic ...
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... Load) RCKH F = 250 MHz MAX Hardwired Clock t = 1.0 ns HCKH F = 320 MHz HMAX Note: Values shown for A54SX08-3, worst-case commercial conditions. Figure 1-12 • SX Timing Model Hardwired Clock External Setup = INY IRD1 SUD = 1.5 + 0.3 + 0.5 – 1.0 = 1.3 ns Clock-to-Out (Pin-to-Pin HCKH ...
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SX Family FPGAs GND 50% 50 Out 1 DLH DHL Figure 1-13 • Output Buffer Delays Load 1 (used to measure propagation delay) To Output Under Test 35 pF Figure ...
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Register Cell Timing Characteristics D t SUD CLK Q CLR PRESET Figure 1-17 • Flip-Flops Timing Characteristics Timing characteristics for SX devices fall into three categories: family-dependent, device-dependent, and design-dependent. The input characteristics are common to all SX family members. ...
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... SX Family FPGAs A54SX08 Timing Characteristics Table 1-17 • A54SX08 Timing Characteristics (Worst-Case Commercial Conditions, V Parameter Description 1 C-Cell Propagation Delays t Internal Array Module PD 2 Predicted Routing Delays Routing Delay, Direct Connect Routing Delay, Fast Connect Routing Delay RD1 ...
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... Table 1-17 • A54SX08 Timing Characteristics (Continued) (Worst-Case Commercial Conditions, V Parameter Description Dedicated (Hardwired) Array Clock Network t Input LOW to HIGH (pad to R-Cell input) HCKH t Input HIGH to LOW (pad to R-Cell input) HCKL t Minimum Pulse Width HIGH HPWH t Minimum Pulse Width LOW HPWL t Maximum Skew ...
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SX Family FPGAs A54SX16 Timing Characteristics Table 1-18 • A54SX16 Timing Characteristics (Worst-Case Commercial Conditions, V Parameter Description 1 C-Cell Propagation Delays t Internal Array Module PD 2 Predicted Routing Delays Routing Delay, Direct Connect DC ...
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Table 1-18 • A54SX16 Timing Characteristics (Continued) (Worst-Case Commercial Conditions, V Parameter Description Dedicated (Hardwired) Array Clock Network t Input LOW to HIGH (pad to R-Cell input) HCKH t Input HIGH to LOW (pad to R-Cell input) HCKL t Minimum ...
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SX Family FPGAs A54SX16P Timing Characteristics Table 1-19 • A54SX16P Timing Characteristics (Worst-Case Commercial Conditions, V Parameter Description 1 C-Cell Propagation Delays t Internal Array Module PD 2 Predicted Routing Delays Routing Delay, Direct Connect DC ...
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Table 1-19 • A54SX16P Timing Characteristics (Continued) (Worst-Case Commercial Conditions, V Parameter Description Dedicated (Hardwired) Array Clock Network t Input LOW to HIGH (pad to R-Cell input) HCKH t Input HIGH to LOW (pad to R-Cell input) HCKL t Minimum ...
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SX Family FPGAs Table 1-19 • A54SX16P Timing Characteristics (Continued) (Worst-Case Commercial Conditions, V Parameter Description TTL/PCI Output Module Timing t Data-to-Pad LOW to HIGH DLH t Data-to-Pad HIGH to LOW DHL t Enable-to-Pad ENZL t Enable-to-Pad, ...
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A54SX32 Timing Characteristics Table 1-20 • A54SX32 Timing Characteristics (Worst-Case Commercial Conditions, V Parameter Description 1 C-Cell Propagation Delays t Internal Array Module PD 2 Predicted Routing Delays Routing Delay, Direct Connect ...
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SX Family FPGAs Table 1-20 • A54SX32 Timing Characteristics (Continued) (Worst-Case Commercial Conditions, V Parameter Description Dedicated (Hardwired) Array Clock Network t Input LOW to HIGH (pad to R-Cell input) HCKH t Input HIGH to LOW (pad to R-Cell input) ...
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Pin Description CLKA/B Clock A and B These pins are 3 5.0 V PCI/TTL clock inputs for clock distribution networks. The clock input is buffered prior to clocking the R-cells. If not used, this pin must be set ...
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Package Pin Assignments 84-Pin PLCC Figure 2-1 • 84-Pin PLCC (Top View) Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/rescenter/package/index.html 84-Pin PLCC v3.2 54SX Family FPGAs 2-1 ...
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... I/O 40 PRB, I CCA 42 GND 43 V CCR 44 I/O 45 HCLK 46 I/O 47 I/O 48 I/O 49 I/O 50 I/O 51 I/O 52 TDO, I/O 53 I/O 54 I/O 55 I/O 56 I/O 57 I CCA 60 V CCI 61 GND 62 I/O 63 I/O 64 I/O 65 I/O 66 I CCA 69 GND 70 I/O v3.2 84-Pin PLCC A54SX08 Pin Number Function 71 I/O 72 I/O 73 I/O 74 I/O 75 I/O 76 I/O 77 I/O 78 I/O 79 I/O 80 I/O 81 I/O 82 I/O 83 CLKA 84 CLKB ...
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PQFP 208 1 Figure 2-2 • 208-Pin PQFP (Top View) Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/rescenter/package/index.html. 208-Pin PQFP v3.2 54SX Family FPGAs 2-3 ...
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... TMS CCI CCI I/O 49 I/O 50 I/O 51 I/O 52 I/O 53 I/O 54 I/O 55 I/O 56 I/O 57 I/O 58 I CCR GND CCA GND 64 I/O 65* I/O 66 I/O 67 I/O 68 I/O 69 I/O 70 I/O 71 I/O 72 v3.2 208-Pin PQFP A54SX16, A54SX08 A54SX16P A54SX32 Function Function Function I/O I/O I/O I/O I/O I/O NC I/O I CCI CCI CCI CCA CCA CCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC I/O I/O I/O I/O I/O NC I/O I/O I/O I/O I/O GND GND ...
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... I/O 129 I/O 130 I/O 131 I/O 132 I/O 133 V 134 CCI CCI I/O 135 I/O 136 I/O 137 I/O 138 TDO, I/O 139 I/O 140 GND 141 I/O 142 I/O 143 I/O 144 v3.2 54SX Family FPGAs 208-Pin PQFP A54SX16, A54SX08 A54SX16P A54SX32 Function Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I CCA CCA CCA CCI CCI CCI NC I/O I/O I/O I/O I/O ...
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... CCI CCI I/O 201 I/O 202 I/O 203 I/O 204 I/O 205 I/O 206 I/O 207 I/O 208 I/O I/O I/O I/O I/O I/O I/O CLKA v3.2 208-Pin PQFP A54SX16, A54SX08 A54SX16P A54SX32 Function Function Function CLKB CLKB CLKB CCR CCR CCR GND GND GND CCA CCA CCA GND GND GND PRA, I/O PRA, I/O PRA, I/O ...
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TQFP 144 1 Figure 2-3 • 144-Pin TQFP (Top View) Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/rescenter/package/index.html. 144-Pin TQFP v3.2 54SX Family FPGAs 2-7 ...
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... CCI CCI GND 47 I/O 48 I/O 49 I/O 50 I/O 51 I/O 52 I CCR CCR V 56 CCA CCA I/O 57 I/O 58 I/O 59 I/O 60 I/O 61 I/O 62 I/O 63 GND CCI CCI V 66 CCA CCA I/O 67 I/O 68 I/O 69 I/O 70 I/O 71 GND 72 v3.2 144-Pin TQFP A54SX08 A54SX16P A54SX32 Function Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I CCI CCI CCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O PRB, I/O PRB, I/O I/O ...
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... CCA 99 GND GND 100 I/O I/O 101 GND GND 102 V V CCI CCI 103 I/O I/O 104 I/O I/O 105 I/O I/O 106 I/O I/O 107 I/O I/O 108 I/O I/O A54SX32 A54SX08 Function Pin Number Function GND 109 GND I/O 110 I/O 111 I/O 112 I/O 113 I/O 114 V 115 CCA V 116 CCI GND 117 I/O 118 I/O 119 I/O 120 I/O 121 I/O ...
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Family FPGAs 176-Pin TQFP 176 1 Figure 2-4 • 176-Pin TQFP (Top View) Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/rescenter/package/index.html 176-Pin TQFP v3.2 ...
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... I/O I/O 21 GND GND CCA CCA 23 GND GND 24 I/O I/O 25 I/O I/O 26 I/O I/O 27 I/O I/O 28 I/O I/O 29 I/O I/O 30 I/O I/O 31 I/O I CCI CCI CCA CCA 34 I/O I/O A54SX32 A54SX08 Function Pin Number Function GND 35 TDI, I/O 36 I/O 37 I/O 38 I/O 39 I/O 40 I/O 41 I/O 42 I/O 43 TMS CCI I/O 46 I/O 47 I/O 48 I/O 49 I/O 50 I/O 51 I/O 52 I/O 53 I/O 54 GND CCA GND 57 ...
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... TDO, I/O 121 I/O 122 GND 123 I/O 124 I/O 125 I/O 126 I/O 127 I/O 128 I/O 129 I/O 130 I/O 131 V 132 CCA V 133 CCI CCI I/O 134 I/O 135 I/O 136 v3.2 176-Pin TQFP A54SX16, A54SX08 A54SX16P A54SX32 Function Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND CCA CCA CCA GND GND GND I/O I/O I/O I/O I/O I/O ...
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... I/O I/O 149 I/O I/O 150 I/O I/O 151 I/O I/O 152 CLKA CLKA 153 CLKB CLKB 154 V V CCR CCR 155 GND GND 156 V V CCA CCA A54SX32 A54SX08 Function Pin Number Function I/O 157 PRA, I/O I/O 158 I/O 159 V 160 CCI I/O 161 I/O 162 I/O 163 I/O 164 I/O 165 I/O 166 I/O 167 I/O 168 I/O 169 ...
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Family FPGAs 100-Pin VQFP 100 1 Figure 2-5 • 100-Pin VQFP (Top View) Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/rescenter/package/index.html 100-Pin VQFP v3.2 ...
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... I/O I/O 55 I/O I/O 56 I/O I CCA CCA CCI CCI 59 I/O I/O 60 I/O I/O 61 I/O I/O 62 I/O I/O 63 I/O I/O 64 I/O I/O 65 I/O I/O 66 I/O I CCA CCA 68 GND GND v3.2 54SX Family FPGAs 100-Pin VQFP A54SX16, Pin A54SX08 A54SX16P Number Function Function 69 GND GND 70 I/O I/O 71 I/O I/O 72 I/O I/O 73 I/O I/O 74 I/O I/O 75 I/O I/O 76 I/O I/O 77 I/O I/O 78 I/O I/O 79 I/O I/O 80 I/O I/O 81 I/O I CCI CCI 83 I/O I/O 84 I/O I/O 85 ...
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Family FPGAs 313-Pin PBGA ...
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PBGA 313-Pin PBGA Pin A54SX32 Pin Number Function Number A1 GND AC5 A3 NC AC7 A5 I/O AC9 A7 I/O AC11 A9 I/O AC13 A11 I/O AC15 A13 V AC17 CCR A15 I/O AC19 A17 I/O AC21 A19 I/O ...
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Family FPGAs 313-Pin PBGA Pin A54SX32 Number Function Number H20 I/O H22 V CCI H24 I/O J1 I/O J3 I I/O J11 I/O J13 CLKA J15 I/O J17 I/O J19 I/O J21 GND J23 ...
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PBGA Figure 2-7 • 329-Pin PBGA (Top View) Note For Package Manufacturing and ...
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Family FPGAs 329-Pin PBGA Pin A54SX32 Number Function Number A1 GND AA13 A2 GND AA14 A3 V AA15 CCI A4 NC AA16 A5 I/O AA17 A6 I/O AA18 A7 V AA19 CCI A8 NC AA20 A9 I/O AA21 A10 ...
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PBGA 329-Pin PBGA Pin A54SX32 Pin Number Function Number D3 I/O F22 D4 TCK, I/O F23 I/O G20 D10 I/O G21 D11 V G22 CCA D12 ...
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Family FPGAs 329-Pin PBGA Pin A54SX32 Number Function Number T22 I/O T23 I/O U1 I CCA U4 I/O U20 I/O U21 V CCA U22 I/O U23 I CCI V2 I/O V3 I/O 2 ...
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FBGA Figure 2-8 • 144-Pin FBGA (Top View) Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/rescenter/package/index.html ...
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... CCR F4 I GND J5 F6 GND J6 F7 GND CCI F9 I/O J9 F10 GND J10 F11 I/O J11 F12 I/O J12 v3.2 144-Pin FBGA A54SX08 Pin A54SX08 Function Number Function I/O K1 I/O GND K2 I/O I/O K3 I/O I/O K4 I/O GND K5 I/O GND K6 I/O GND K7 GND V K8 I/O CCI I/O K9 I/O I/O K10 GND I/O K11 I/O I/O K12 ...
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... Information concerning the TRST pin in the The "Dedicated Test Mode" section The "Programming" section A note was added to the A note was added to the following devices: A54SX08, A54SX16, A54SX32. U11 and U13 were added to the v3.0.1 Storage temperature in Table 1-1 was updated. Datasheet Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as " ...
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