EX256-FCS100 ETC1 [List of Unclassifed Manufacturers], EX256-FCS100 Datasheet - Page 20

• Manufacturer Part Number: EX256-FCS100
• Description: eX Family FPGAs
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

Pi n D es c r i pt i on
CLKA/B
These pins are clock inputs for clock distribution networks.
Input levels are compatible with standard TTL or LVTTL
specifications. The clock input is buffered prior to clocking
the R-cells. If not used, this pin must be set LOW or HIGH on
the board. It must not be left floating.
GND
LOW supply voltage.
HCLK
This pin is the clock input for sequential modules. Input
levels are compatible with standard TTL or LVTTL
specifications. This input is directly wired to each R-cell and
offers clock speeds independent of the number of R-cells
being driven. If not used, this pin must be set LOW or HIGH
on the board. It must not be left floating.
I/O
The I/O pin functions as an input, output, tristate, or
bidirectional buffer. Based on certain configurations, input
and output levels are compatible with standard TTL or
LVTTL specifications. Unused I/O pins are automatically
tristated by the Designer Series software.
LP
Controls the low power mode of the eX devices. The device
is placed in the low power mode by connecting the LP pin
to logic high. In low power mode, all I/Os are tristated, all
input buffers are turned OFF, and the core of the devices is
turned OFF. To exit the low power mode, the LP pin must
be set LOW. The device enters the low power mode 800ns
after the LP pin is driven to a logic HIGH. It will resume
normal operation in 200 µ s after the LP pin is driven to a
logic low. The logic high level on the LP pin must never
exceed the V
NC
This pin is not connected to circuitry within the device.
These pins can be driven to any voltage or can be left
floating with no effect on the operation of the device.
PRA, I/O
PRB, I/O
The Probe pin is used to output data from any user-defined
design node within the device. This independent diagnostic
pin can be used in conjunction with the other probe pin to
allow real-time diagnostic output of any signal path within
the device. The Probe pin can be used as a user-defined I/O
when verification has been completed. The pin’s probe
capabilities can be permanently disabled to protect
programmed design confidentiality.
20
SV
voltage. Refer to the V
Ground
Dedicated (Hard-wired)
Array Clock
Input/Output
Low Power Pin
No Connection
Probe A/B
Clock A and B
SV
pin description.
v3.0
TCK, I/O
Test clock input for diagnostic probe and device
programming. In flexible mode, TCK becomes active when
the TMS pin is set LOW (refer to
functions as an I/O when the boundary scan state machine
reaches the “logic reset” state.
TDI, I/O
Serial input for boundary scan testing and diagnostic probe.
In flexible mode, TDI is active when the TMS pin is set LOW
(refer to
when the boundary scan state machine reaches the “logic
reset” state.
TDO, I/O
Serial output for boundary scan testing. In flexible mode,
TDO is active when the TMS pin is set LOW (refer to
on page
scan state machine reaches the "logic reset" state. When
Silicon Explorer is being used, TDO will act as an output
when the "checksum" command is run. It will return to user
IO when "checksum" is complete.
TMS
The TMS pin controls the use of the IEEE 1149.1 Boundary
Scan pins (TCK, TDI, TDO, TRST). In flexible mode when
the TMS pin is set LOW, the TCK, TDI, and TDO pins are
boundary scan pins (refer to
boundary scan pins are in test mode, they will remain in that
mode until the internal boundary scan state machine
reaches the “logic reset” state. At this point, the boundary
scan pins will be released and will function as regular I/O
pins. The “logic reset” state is reached 5 TCK cycles after
the TMS pin is set HIGH. In dedicated test mode, TMS
functions as specified in the IEEE 1149.1 specifications.
TRST, I/O
Once it is configured as the JTAG Reset pin, the TRST pin
functions as an active-low input to asynchronously initialize
or reset the boundary scan circuit. The TRST pin is equipped
with an internal pull-up resistor. This pin functions as an I/O
when the “Reserve JTAG Reset Pin” is not selected in
Designer.
V
Supply voltage for I/Os. See
V
Supply voltage for Array. See
V
Supply voltage used for device programming. This pin can be
tied to V
fuse is programmed, the V
C CI
C CA
S V
6). This pin functions as an I/O when the boundary
CCA
Table 3 on page
or V
CCI
Test Clock
Test Data Input
Test Data Output
Test Mode Select
Boundary Scan Reset Pin
Supply Voltage
Supply Voltage
Programming Voltage
but cannot exceed 3.6V. If the security
SV
6). This pin functions as an I/O
Table 2 on page
limit is extended to 6.0V.
Table 2 on page
Table 3 on page
Table 3 on page
e X F a m il y F P GA s
6.
6.
6). Once the
6). This pin
Table 3