9248AG-195LF Integrated Device Technology, 9248AG-195LF Datasheet
9248AG-195LF
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9248AG-195LF Summary of contents
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Integrated Circuit Systems, Inc. Frequency Generator & Integrated Buffers for PENTIUM II III Recommended Application: 440BX, MX, VIA PM/PL/PLE 133 style chip set, with Coppermine or Tualatin processor, for note book applications. Output Features: • CPUs @ 2.5V/3.3V ...
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ICS9248-195 Pin Descriptions ...
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General Description The ICS9248-195 is the single chip clock solution for Notebook designs using the 440BX, MX, VIA PM/PL/PLE 133 style chip set, with Coppermine or Tualatin processor, for Note book applications. It provides all necessary clock signals for such ...
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ICS9248-195 Byte 1: Active/Inactive Register (1 = enable disable ...
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Byte 4: Active/Inactive Register (1 = enable disable ...
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ICS9248-195 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Logic Inputs . . . . . . . ...
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Electrical Characteristics - CPU 70° 3.3 V +/-5 PARAMETER SYMBOL Output High Voltage V OH2A Output Low Voltage V OL2A Output High Current I OH2A Output Low Current I OL2A 1 ...
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ICS9248-195 Electrical Characteristics - PCI 70° 3.3 V +/-5 PARAMETER SYMBOL Output High Voltage V OH1 Output Low Voltage V OL1 Output High Current I OH1 Output Low Current I OL1 ...
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Electrical Characteristics - 24,48MHz 70° 3.3 V +/-5 PARAMETER SYMBOL Output High Voltage V OH5 Output Low Voltage V OL5 Output High Current I OH5 Output Low Current I OL5 1 ...
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ICS9248-195 General I The information in this section assumes familiarity with I For more information, contact ICS for an I How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D2 • ICS ...
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Shared Pin Operation - Input/Output Pins The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this ...
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ICS9248-195 PD# Timing Diagram The power down selection is used to put the part into a very low power state without turning off the power to the part. PD asynchronous active low input. This signal needs to be ...
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CLK_STOP# Timing Diagram CLK_STOP asychronous input to the clock synthesizer used to turn off the CPU clocks for low power operation. CLK_STOP# is synchronized by the ICS9248-195. The minimum that the CPU clock is enabled (CLK_STOP# ...
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ICS9248-195 PCI_STOP# Timing Diagram PCI_STOP asynchronous input to the ICS9248-195 used to turn off the PCICLK clocks for low power operation. PCI_STOP# is synchronized by the ICS9248-195 internally. The minimum that the PCICLK clocks are enabled ...
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INDEX INDEX AREA AREA 45° 45° SEATING SEATING b PLANE PLANE .10 (.004) C .10 (.004) C 300 mil SSOP Package Ordering Information ICS9248yF-195LF-T Example: ...