S912XEP100J5MAGR Freescale Semiconductor, S912XEP100J5MAGR Datasheet - Page 1012
S912XEP100J5MAGR
Manufacturer Part Number
S912XEP100J5MAGR
Description
S912XEP Series 16 Bit 50 Mhz 1 MB Flash 64 KB Ram Microcontroller - LQFP-144
Manufacturer
Freescale Semiconductor
Datasheet
1.S912XEP100J5MAG.pdf
(1328 pages)
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Chapter 26 384 KByte Flash Module (S12XFTM384K2V1)
The D-Flash user partition will start at global address 0x10_0000. The buffer RAM EEE partition will end
at global address 0x13_FFFF. After the Partition D-Flash operation has completed, the CCIF flag will set.
Running the Partition D-Flash command a second time will result in the ACCERR bit within the FSTAT
register being set. The data value written corresponds to the number of 256 byte sectors allocated for either
direct D-Flash access (DFPART) or buffer RAM EEE access (ERPART).
1012
•
•
•
FERSTAT
Program a duplicate DFPART to the EEE nonvolatile information register at global address
0x12_0002 (see
Program ERPART to the EEE nonvolatile information register at global address 0x12_0004 (see
Table
Program a duplicate ERPART to the EEE nonvolatile information register at global address
0x12_0006 (see
Register
FSTAT
26-7)
MGSTAT1
MGSTAT0
EPVIOLIF
ACCERR
Error Bit
FPVIOL
Table
Table
Table 26-78. Partition D-Flash Command Error Handling
26-7)
26-7)
MC9S12XE-Family Reference Manual , Rev. 1.23
Set if CCOBIX[2:0] != 010 at command launch
Set if a Load Data Field command sequence is currently active
Set if command not available in current mode (see
Set if partitions have already been defined
Set if an invalid DFPART or ERPART selection is supplied
None
Set if any errors have been encountered during the read
Set if any non-correctable errors have been encountered during the read
None
Error Condition
Table
26-30)
Freescale Semiconductor
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