S912XEP100J5MAGR Freescale Semiconductor, S912XEP100J5MAGR Datasheet - Page 390
S912XEP100J5MAGR
Manufacturer Part Number
S912XEP100J5MAGR
Description
S912XEP Series 16 Bit 50 Mhz 1 MB Flash 64 KB Ram Microcontroller - LQFP-144
Manufacturer
Freescale Semiconductor
Datasheet
1.S912XEP100J5MAG.pdf
(1328 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S912XEP100J5MAGR
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
- Current page: 390 of 1328
- Download datasheet (9Mb)
Chapter 10 XGATE (S12XGATEV3)
10.8.4
When the RISC core is triggered by an interrupt request (see
sequence which performs three bus accesses:
Afterwards a sequence of instructions (thread) is executed which is terminated by an "RTS" instruction. If
further interrupt requests are pending after a thread has been terminated, a new vector fetch will be
performed. Otherwise the RISC core will either resume a previous thread (beginning with a P-cycle to
refetch the interrupted opcode) or it will become idle until a new interrupt request is received. A thread can
only be interrupted by an interrupt request of higher priority.
10.8.5
This section describes the XGATE instruction set in alphabetical order.
390
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
1. A V-cycle to fetch the initial content of the program counter.
2. A V-cycle to fetch the initial content of the data segment pointer (R1).
3. A P-cycle to load the initial opcode.
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
V — Vector fetch: always an aligned word read, lasts for at least one RISC core cycle
P — Program word fetch: always an aligned word read, lasts for at least one RISC core cycle
r — 8 bit data read: lasts for at least one RISC core cycle
R — 16 bit data read: lasts for at least one RISC core cycle
w — 8 bit data write: lasts for at least one RISC core cycle
W — 16 bit data write: lasts for at least one RISC core cycle
A — Alignment cycle: no read or write, lasts for zero or one RISC core cycles
f — Free cycle: no read or write, lasts for one RISC core cycles
Special Cases
PP/P — Branch: PP if branch taken, P if not
Thread Execution
Instruction Glossary
MC9S12XE-Family Reference Manual , Rev. 1.23
Table 10-23. Access Detail Notation
Figure
10-1) it first executes a vector fetch
Freescale Semiconductor
Related parts for S912XEP100J5MAGR
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
Manufacturer:
Freescale Semiconductor, Inc
Datasheet:
Part Number:
Description:
Manufacturer:
Freescale Semiconductor, Inc
Datasheet:
Part Number:
Description:
Manufacturer:
Freescale Semiconductor, Inc
Datasheet:
Part Number:
Description:
Manufacturer:
Freescale Semiconductor, Inc
Datasheet:
Part Number:
Description:
Manufacturer:
Freescale Semiconductor, Inc
Datasheet:
Part Number:
Description:
Manufacturer:
Freescale Semiconductor, Inc
Datasheet:
Part Number:
Description:
Manufacturer:
Freescale Semiconductor, Inc
Datasheet:
Part Number:
Description:
Manufacturer:
Freescale Semiconductor, Inc
Datasheet:
Part Number:
Description:
Manufacturer:
Freescale Semiconductor, Inc
Datasheet:
Part Number:
Description:
Manufacturer:
Freescale Semiconductor, Inc
Datasheet:
Part Number:
Description:
Manufacturer:
Freescale Semiconductor, Inc
Datasheet:
Part Number:
Description:
Manufacturer:
Freescale Semiconductor, Inc
Datasheet:
Part Number:
Description:
Manufacturer:
Freescale Semiconductor, Inc
Datasheet:
Part Number:
Description:
Manufacturer:
Freescale Semiconductor, Inc
Datasheet:
Part Number:
Description:
Manufacturer:
Freescale Semiconductor, Inc
Datasheet: