93LC46B-I/MSG Microchip, 93LC46B-I/MSG Datasheet - Page 6

• Manufacturer Part Number: 93LC46B-I/MSG
• Description: ind, Semiconductors and Actives, serial, Memory
• Manufacturer: Microchip

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
2.4
The ERASE instruction forces all data bits of the
specified address to the logical ‘1’ state. CS is brought
low following the loading of the last address bit. This
falling edge of the CS pin initiates the self-timed
programming cycle, except on ‘93C’ devices where the
rising edge of CLK before the last address bit initiates
the write cycle.
FIGURE 2-1:
FIGURE 2-2:
DS21749D-page 6
CLK
CLK
DO
DO
CS
DI
CS
DI
ERASE
HIGH-Z
HIGH-Z
1
1
ERASE TIMING FOR 93AA AND 93LC DEVICES
ERASE TIMING FOR 93C DEVICES
1
1
1
1
A
A
N
N
A
A
N
N
-1
-1
A
A
N
N
-2
-2
•••
•••
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (T
is still in progress. DO at logical ‘1’ indicates that the
register at the specified address has been erased and
the device is ready for another instruction.
A0
A0
Note:
T
T
CSL
CSL
CSL
). DO at logical ‘0’ indicates that programming
Issuing a Start bit and then taking CS low
will clear the READY/BUSY status from
DO.
T
WC
T
T
T
SV
WC
SV
CHECK STATUS
CHECK STATUS
BUSY
BUSY
 2003 Microchip Technology Inc.
READY
READY
HIGH-Z
HIGH-Z
T
T
CZ
CZ