LFE2-6E-5TN144CES Lattice Semiconductor, LFE2-6E-5TN144CES Datasheet - Page 266
LFE2-6E-5TN144CES
Manufacturer Part Number
LFE2-6E-5TN144CES
Description
Semiconductors and Actives, programmable, Programmable Logic (FPGAs, PALs, CPLDs ...), gate
Manufacturer
Lattice Semiconductor
Datasheet
1.LFE26E5TN144C.pdf
(385 pages)
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Lattice Semiconductor
LFE2M50E/SE Logic Signal Connections: 484 fpBGA (Cont.)
* Supports true LVDS. Other differential signals must be emulated with external resistors.
** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant.
***Due to packaging bond out option, this DQS does not have all the necessary DQ pins bonded out for a full 8-bit data width.
Note: VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the
last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one
connection with a package ball or pin.
Ball Number
W19
W18
G14
G15
G12
G13
V17
V18
D15
D14
E15
E14
H15
R15
F15
F14
F13
H8
R8
Ball/Pad Function
VCCPLL
VCCPLL
VCCPLL
VCCPLL
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
LFE2M50E/SE
4-166
Bank
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LatticeECP2/M Family Data Sheet
Dual Function
Pinout Information
Differential
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