MT47H64M16HR-25E AIT:H Micron, MT47H64M16HR-25E AIT:H Datasheet - Page 36

• Manufacturer Part Number: MT47H64M16HR-25E AIT:H
• Description: Ic Ddr2 Sdram 1gbit 84fbga
• Manufacturer: Micron

18. The inputs to the DRAM must be aligned to the associated clock, that is, the actual clock that latches it in. Howev-
19. The DRAM output timing is aligned to the nominal or average clock. Most output parameters must be derated by
20. When DQS is used single-ended, the minimum limit is reduced by 100ps.
21.
22.
23. This is not a device limit. The device will operate with a negative value, but system performance could be degra-
24. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS go-
25. The intent of the “Don’t Care” state after completion of the postamble is that the DQS-driven signal should either
26. Referenced to each output group: x4 = DQS with DQ[3:0]; x8 = DQS with DQ[7:0]; x16 = LDQS with DQ[7:0]; and
27. The data valid window is derived by achieving other specifications:
28.
29. This maximum value is derived from the referenced test load.
30. The values listed are for the differential DQS strobe (DQS and DQS#) with a differential slew rate of 2 V/ns (1 V/ns
er, the input timing (in ns) references to the
lowing input parameters are determined by taking the specified percentage times the
t
the actual jitter error when input clock jitter is present; this will result in each parameter becoming larger. The
following parameters are required to be derated by subtracting
(MIN),
t
t
The parameter
t
however, the total window will not degrade.
t
referenced to a specific voltage level, but specify when the device output is no longer driving (
ing (
t
ded due to bus turnaround.
ing from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous
WRITE was in progress, DQS could be HIGH during this time, depending on
be HIGH, LOW, or High-Z, and that any signal transition within the input switching region must follow valid input
requirements. That is, if DQS transitions HIGH (above V
prior to
UDQS with DQ[15:8].
The data valid window derates in direct proportion to the clock duty cycle and a practical data valid window can
be derived.
t
-
will provide a larger valid data out window.
(MAX) condition.
for each signal). There are two sets of values listed:
only) are equivalent to the baseline values of
baseline values,
from V
nal and V
must be derated by adding the values from Table 30 (page 58) and Table 31 (page 59). If the DQS differential
strobe feature is not enabled, then the DQS strobe is single-ended and the baseline values must be derated using
IPW,
ERR
RPRE (MIN) is derated by subtracting
JITdty (MIN). Output timings that require
HZ and
LZ (MIN) will prevail over a
QH =
t
QHS. Minimizing the amount of
5per
t
LZ).
t
DIPW,
t
t
IH(AC)
HP -
LZ
t
(MIN):
t
DQSH (MIN).
LZ transitions occur in the same access time windows as valid data transitions. These parameters are not
IH(DC)
DQ
t
QHS; the worst case
for a rising signal and V
t
(MIN),
DQSS,
for a falling signal. If the differential DQS slew rate is not equal to 2 V/ns, then the baseline values
t
t
AC (MAX),
RPST (MIN) is derated by subtracting
t
DS
t
b
t
AON (MIN); while the following parameters are required to be derated by subtracting
,
DQSH,
t
DH
b
, are the JEDEC-defined values, referenced from the logic trip points.
t
t
DQSCK (MAX),
t
DQSL,
DQSCK (MIN) +
t
QH would be the lesser of
t
t
CH (AVG) offset and value of
DSS,
IL(AC)
t
JITper (MAX), while
t
DSH,
for a falling signal, while
t
t
ERR
HZ (MAX),
t
t
CK (AVG) when determining the required number of clocks. The fol-
RPRE (MAX) condition.
t
t
DS
5per
WPST, and
b
,
derating can be observed to have offsets relative to the clock;
t
t
DH
DS
t
JITdty (MAX), while
t
b
LZ
IH[DC]min
a
,
at V
t
DQS
DH
t
WPRE.
t
RPRE (MAX), is derated by subtracting
t
CL (ABS) MAX or
REF
a
(MAX),
t
and
HZ (MAX) will prevail over
), then it must not transition LOW (below V
when the slew rate is 2 V/ns, differentially. The
t
t
ERR
JITdty will provide a larger
t
t
t
DS
DH
HP (
5per
t
LZ
b
b
,
DQ
t
t
is referenced from V
CK/2),
DH
(MAX):
t
RPST (MAX), is derated by subtracting
(MAX),
t
b
DQSS.
. The
t
CH (ABS) MAX times
t
DQSQ, and
t
AC (MIN),
t
t
AON (MAX). The parameter
DS
a
,
t
CK (AVG) rather than
t
DH
t
DQSCK (MAX) +
t
t
a
DQSCK (MIN),
QH (
t
IL(DC)
values (for reference
QH, which in turn
t
HZ) or begins driv-
t
DS
t
QH =
for a rising sig-
t
JITper (MIN).
b
t
CK (ABS) MIN
is referenced
t
HP -
IH[DC]
t
t
LZ
RPST
t
QHS).
t
DQS
CK:
)