HC55185EVAL1 Intersil, HC55185EVAL1 Datasheet - Page 7

• Manufacturer Part Number: HC55185EVAL1
• Manufacturer: Intersil

Digital Loop Back Configuration
Description
The digital loop back configuration verifies the interface and
operation of the HC55185 device and the CODEC. This
configuration provides a self test to verify proper operation of
the board. In addition, it provides a complete digital loop,
allowing analog control of the digital input and output of the
CODEC. Forward active and reverse active or teletax will
support the digital loop back configuration.
Power Supply Connections
Power should be applied to the evaluation board using the
primary power cable. Either J5 or J6 may be used. Prior to
applying power, the voltage setting of each supply should be
verified. The power supplies should be turned off while
mating the primary power cable to the evaluation board.
Jumper Settings
All jumper settings and functions are described below.
JP10, POSN 2 Sets the CODEC master clock to 512kHz.
J14, POSN 1
JUMPER
TABLE 3. DIGITAL LOOP BACK JUMPER POSITIONS
JP11
JP12
JP6
Connects the device transmit output VTX to the
CODEC amplifier for transhybrid balance.
Enables the on board logic multiplexer.
Inserting jumper selects on board clock and frame
sync generator.
Connects the CODEC digital output DT to digital
input DR.
4-7
J3
J2
DESCRIPTION
J4
FIGURE 6. DIGITAL LOOP BACK CONNECTORS AND JUMPERS
J1
S1
0
JP1
S2
0
J5
JP2
S3
APP CKT
HC55185
1
JP3
Application Note 9814
S4
x
S5
1
J6
S6
JP4
0
JP6
JP5
CLOCK GENERATION & MUX
J7
JP9
Signal Flow
Driving a signal at VREC, J8, will result in a signal from the
CODEC receive output when the HC55185 device is
terminated at Tip and Ring. The following diagram shows the
signal path formed by the jumpers and terminated SLIC.
With VREC input signal level of 0.775V
0.337V
with 600 . The signal level at VTX is determined by the
4-wire to 4-wire gain, G
balance is not connected, therefore, the digitized signal level
at the CODEC will be approximately 0.674V
CODEC transfer functions are set for unity gain, therefore
the signal level at PO- should be approximately 0.674V
The signal levels for digital loop back are independent of the
clock selected by JP10.
Refer to the device electrical data sheet for the design
equations for the 4-wire to 4-wire gain as a function of
termination and synthesized impedance.
600
JP8
J8
JP10
RMS
FIGURE 7. DIGITAL LOOP BACK SIGNAL FLOW
APP CKT
CODEC
TIP
RING
JP12
JP11
HC55185
should result at the VTX output when terminated
J9
J15
VRX
VTX
JP7
VREC (J8)
J10
J11
J12
J13
44
J14
JP6
, of the HC55185. The transhybrid
-2
JP4
RMS
PO-
TG
CODEC
, a signal level of
RMS
. The
DR
DT
RMS
J14
.