FM24CL04-GTR Ramtron, FM24CL04-GTR Datasheet
FM24CL04-GTR
Related parts for FM24CL04-GTR
FM24CL04-GTR Summary of contents
Page 1
... The FM24CL04 provides substantial benefits to users of serial EEPROM, yet these benefits are available in a hardware drop-in replacement. The FM24CL04 is available in an industry standard 8-pin package using a two-wire protocol. ...
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... Write Protect: When WP is high the entire array is write protected. When WP is low, all addresses may be written. This pin is internally pulled down connect VDD Supply Supply Voltage VSS Supply Ground Rev. 3.0 March 2005 Address Latch Figure 1. Block Diagram FM24CL04 128 x 32 FRAM Array 8 Data Latch Page ...
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... This is explained in more detail in the interface section below. Users can expect several obvious system benefits from the FM24CL04 due to its fast write cycle and high endurance as compared with EEPROM. However there are less obvious benefits as well. For example in a high noise environment, the fast-write operation is less susceptible to corruption than an EEPROM since it is completed quickly ...
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... When a read operation is complete and no more data is needed, the receiver must not acknowledge acknowledges the last byte, this will cause the FM24CL04 to attempt to drive the bus on the next clock while the master is sending a new command such as a Stop command. Slave Address The first byte that the FM24CL04 expects after a start condition is the slave address ...
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... After all address information has been transmitted, data transfer between the bus master and the FM24CL04 can begin. For a read operation the FM24CL04 will place 8 data bits on the bus then wait for an acknowledge. If the acknowledge occurs, the next sequential byte will be transferred. If the acknowledge is not sent, the read operation is concluded ...
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... FM24CL04 should read out the next sequential byte. There are four ways to properly terminate a read operation. Failing to properly terminate the read will most likely create a bus contention as the FM24CL04 Rev. 3.0 March 2005 Address & Data 0 A Word Address Acknowledge Figure 5 ...
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... Rev. 3.0 March 2005 Figure 7. Current Address Read Figure 8. Sequential Read Figure 9. Selective (Random) Read FM24CL04 Page ...
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... Std JESD22-A114-B) (JEDEC Std JESD22-A115-A) = 2.7V to 3.65V unless otherwise specified) DD Min 2 other inputs -0. Stop command issued FM24CL04 Ratings -1.0V to +5.0V -1.0V to +5.0V and V < V +1. - 125 C 300 C 3kV 300V MSL-1 Typ Max Units Notes 3. 150 ...
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... Min 0 100 0 4.7 1.3 4.0 0.6 3 4.7 1.3 4.0 0.6 4.7 0 250 100 1000 300 4.0 0 3V) DD Max Units FM24CL04 Max Min Max Units Notes 400 0 1000 kHz 0.6 s 0.4 s 0.9 0.55 s 0.5 s 0. 100 ns 300 300 ns 1 300 100 ...
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... Write timing parameters apply to slave address, word address, and write data bits. Functional relationships are illustrated in the relevant data sheet sections. These diagrams illustrate the timing parameters only. Read Bus Timing Write Bus Timing Data Retention (V = 2.7V to 3.65V, +85°C) DD Parameter Data Retention Rev. 3.0 March 2005 Min Units Notes 45 Years FM24CL04 Page ...
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... SOIC Package Marking Scheme Legend: XXXX= part number, P= package type LLLLLLL= lot code XXXXXXX-P LLLLLLL RIC=Ramtron Int’l Corp, YY=year, WW=work week RICYYWW Example: FM24CL04, Standard SOIC package, Year 2004, Work Week 39 FM24CL04-S A40003S RIC0439 Rev. 3.0 March 2005 Recommended PCB Footprint 3.90 ...