5V9950PFI IDT, 5V9950PFI Datasheet

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5V9950PFI

Manufacturer Part Number
5V9950PFI
Description
Clock Drivers & Distribution 3.3V Turbo Clock II Jr.
Manufacturer
IDT
Type
PLL Clock Driversr
Datasheet

Specifications of 5V9950PFI

Multiply / Divide Factor
1
Output Type
LVTTL
Max Output Freq
200 MHz
Supply Voltage - Max
3.6 V
Supply Voltage - Min
3 V
Maximum Operating Temperature
+ 85 C
Package / Case
TQFP-32
Maximum Power Dissipation
1.1 W
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Current
125 mA
Part # Aliases
IDT5V9950PFI
FEATURES:
• Ref input is 5V tolerant
• 4 pairs of programmable skew outputs
• Low skew: 185ps same pair, 250ps all outputs
• Selectable positive or negative edge synchronization:
• Synchronous output enable
• Input frequency: 6MHz to 200MHz
• Output frequency: 6MHz to 200MHz
• 2x, 4x, 1/2, and 1/4 outputs
• 3-level inputs for skew and PLL range control
• PLL bypass for DC testing
• External feedback, internal loop filter
• 12mA balanced drive outputs
• Low Jitter: <100ps cycle-to-cycle
• Available in TQFP package
• Not Recommended for New Design
FUNCTIONAL BLOCK DIAGRAM
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
IDT5V9950
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II
JR.
c
Excellent for DSP applications
2012 Integrated Device Technology, Inc.
REF
FB
PE TEST
3.3V PROGRAMMABLE SKEW
PLL CLOCK DRIVER
TURBOCLOCK™ II JR.
PLL
FS
3
3
1
3
3
3
3
Select
Select
Select
Select
Skew
Skew
Skew
Skew
DESCRIPTION:
for high performance computing and data-communications applica-
tions. A key feature of the programmable skew is the ability of outputs
to lead or lag the REF input signal. The IDT5V9950 has eight program-
mable skew outputs in four banks of 2. Skew is controlled by 3-level
input signals that may be hard-wired to appropriate HIGH-MID-LOW
levels.
enabled. However, if sOE is held high, all the outputs except 2Q0 and
2Q1 are synchronously disabled.
with the positive edge of the REF clock input. When PE is held low, all
the outputs are synchronized with the negative edge of REF. The
IDT5V9950 has LVTTL outputs with 12mA balanced drive outputs.
The IDT5V9950 is a high fanout 3.3V PLL based clock driver intended
When the sOE pin is held low, all the outputs are synchronously
Furthermore, when PE is held high, all the outputs are synchronized
3
3
3
3
1F1:0
2F1:0
3F1:0
4F1:0
sOE
INDUSTRIAL TEMPERATURE RANGE
1Q
1Q
2Q
2Q
3Q
3Q
4Q
4Q
0
1
0
1
0
1
0
1
IDT5V9950
JULY 2012
NRND
DSC 5870/7

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5V9950PFI Summary of contents

Page 1

... A key feature of the programmable skew is the ability of outputs to lead or lag the REF input signal. The IDT5V9950 has eight program- mable skew outputs in four banks of 2. Skew is controlled by 3-level input signals that may be hard-wired to appropriate HIGH-MID-LOW levels ...

Page 2

... IDT5V9950 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR. PIN CONFIGURATION DDQ GND TQFP TOP VIEW PIN DESCRIPTION Pin Name Type Description REF IN Reference Clock Input FB IN ...

Page 3

... Range and Resolution Table). There are nine skew configurations available for each output pair. These configurations are chosen by EXTERNAL FEEDBACK By providing external feedback, the IDT5V9950 gives users flex- ibility with regard to skew adjustment. The FB signal is compared with the input REF signal at the phase detector in order to drive the VCO ...

Page 4

... IDT5V9950 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR. CONTROL SUMMARY TABLE FOR FEEDBACK SIGNALS nF1:0 ( NOTES disables outputs if TEST = MID and sOE = HIGH. 2. When pair #4 is set to HH (inverted), sOE disables pair #4 HIGH when PE = HIGH, sOE disables pair #4 LOW when PE = LOW. ...

Page 5

... F t Input clock pulse, HIGH or LOW PWC D Input duty cycle H F Reference clock input frequency REF NOTE: 1. Where pulse width implied less than t H PWC Test Conditions V = Max., TEST = MID, REF = LOW LOW, sOE = LOW MID All outputs unloaded Max ...

Page 6

... PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR. SWITCHING CHARACTERISTICS OVER OPERATING RANGE Symbol Parameter F VCO Frequency Range NOM t REF Pulse Width HIGH (1) RPWH t REF Pulse Width LOW (1) RPWL t Programmable Skew Time Unit U t Zero Output Matched-Pair Skew (xQ SKEWPR t Zero Output Skew (All Outputs) SKEW0 t ...

Page 7

... IDT5V9950 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR. AC TEST LOADS AND WAVEFORMS  150 Output  150 LVTTL Output Waveform  1ns 3.0V 2. 1.5V TH 0.8V 0V LVTTL Input Test Waveform 7 INDUSTRIAL TEMPERATURE RANGE 20pF  ...

Page 8

... The skew between outputs when they are selected for 0t SKEW0 t : The output-to-output skew between any two devices operating under the same conditions (V DEV t : The deviation of the output from a 50% duty cycle. Output pulse width variations are included in t ODCV t is measured at 2V. PWH t is measured at 0.8V. PWL ...

Page 9

... Silver Creek Valley Road San Jose, CA 95138 X Package I PF PFG 5V9950 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com 9 INDUSTRIAL TEMPERATURE RANGE -40°C to +85°C (Industrial) Thin Quad Flat Pack TQFP - Green 3.3V Programmable Skew PLL Clock Driver TurboClock II Jr. for Tech Support: clockhelp@idt.com ...

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