5V9950PFI IDT, 5V9950PFI Datasheet - Page 6

• Manufacturer Part Number: 5V9950PFI
• Description: Clock Drivers & Distribution 3.3V Turbo Clock II Jr.
• Manufacturer: IDT
• Type: PLL Clock Driversr

Specifications of 5V9950PFI

• Multiply / Divide Factor: 1
• Output Type: LVTTL
• Max Output Freq: 200 MHz
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 3 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-32
• Maximum Power Dissipation: 1.1 W
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Current: 125 mA
• Part # Aliases: IDT5V9950PFI

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
NOTES:
1. Refer to Input Timing Requirements table for more detail.
2. Skew is the time between the earliest and the latest output transition among all outputs for which the same t
3. t
4. t
5. There are 3 classes of outputs: Nominal (multiple of t
6. t
7. tφ is measured with REF input rise and fall times (from 0.8V to 2V) of 0.5ns. Measured from 1.5V on REF to 1.5V on FB.
8. Measured at 2V.
9. Measured at 0.8V.
10. t
IDT5V9950
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II
JR.
Symbol
t
SKEWPR
t
t
t
t
t
t
t
t
F
t
SKEW0
SKEW1
SKEW2
SKEW3
SKEW4
t
t
t
Test condition: nF0:1=MM is set on unused outputs.
from the application of a new signal or frequency at REF or FB until t
t
RPWH
t
ORISE
OFALL
t
RPWL
ODCV
t
SKEWPR
SK(0)
DEV
LOCK
t
LOCK
CCJH
CCJM
CCJL
PWH
PWL
DEV
t
NOM
t
(φ)
U
is the output-to-output skew between any two devices operating under the same conditions (V
is the skew between outputs when they are selected for 0t
is the time that is required before synchronization is achieved. This specification is valid only after V
is the skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0t
Parameter
VCO Frequency Range
REF Pulse Width HIGH
REF Pulse Width LOW
Programmable Skew Time Unit
Zero Output Matched-Pair Skew (xQ
Zero Output Skew (All Outputs)
Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs)
Output Skew (Rise-Fall, Nominal-Inverted, Divided-Divided)
Output Skew (Rise-Rise, Fall-Fall, Different Class Outputs)
Output Skew (Rise-Fall, Nominal-Divided, Divided-Inverted)
Device-to-Device Skew
REF Input to FB Static Phase Offset)
Output Duty Cycle Variation from 50%
Output HIGH Time Deviation from 50%
Output LOW Time Deviation from 50%
Output Rise Time
Output Fall Time
PLL Lock Time
Cycle-to-Cycle Output Jitter (peak-to-peak)
(divide by 1 output frequency, FS = H, FB divide-by-n=1,2)
Cycle-to-Cycle Output Jitter (peak-to-peak)
(divide by 1 output frequency, FS = M)
Cycle-to-Cycle Output Jitter (peak-to-peak)
(divide by 1 output frequency, FS = L, F
(10)
(1)
(2,6)
(1)
(4)
U
delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in Divide-by-2 or Divide-by-4 mode).
0
(7)
, xQ
(9)
(8)
REF
1
)
(2,3)
> 3MHz)
U
.
PD
is within specified limits.
(5)
(5)
(5)
(2)
6
DDQ
, V
U
DD
.
DD
/V
DDQ
, ambient temperature, air flow, etc.)
U
−
Min.
0.15
0.15
delay has been selected when all are loaded with the specified load.
−
—
—
—
—
—
—
—
0.25
—
—
—
—
—
—
2
2
is stable and within normal operating limits. This parameter is measured
See Programmable Skew Range and Resolution Table
1
See Control Summary Table
INDUSTRIAL TEMPERATURE RANGE
Typ.
0.15
0.1
0.1
0.2
0.3
0.7
0.7
50
—
—
—
—
—
—
—
—
—
—
0
Max.
0.25
0.25
0.75
0.25
185
100
150
200
0.5
0.5
0.9
1.5
1.5
1.5
0.5
—
—
1
2
Unit
ms
ns
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps