83947AYILNT IDT, 83947AYILNT Datasheet
83947AYILNT
Specifications of 83947AYILNT
Related parts for 83947AYILNT
83947AYILNT Summary of contents
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... CLK_EN D Q LVCMOS_CLK 1 CLK 0 nCLK CLK_SEL OE IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR Features • Twelve LVCMOS/LVTTL outputs • Selectable differential CLK/nCLK or LVCMOS/LVTTL clock input • CLK/nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • ...
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... Table 3A. Clock Select Function Table Control Clock Input 0 CLK/nCLK inputs selected 1 LVCMOS_CLK input selected IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR Type Description Clock select input. When HIGH, selects LVCMOS_CLK input. Input Pullup When LOW, selects CLK/nCLK inputs. LVCMOS / LVTTL interface levels. Input Pullup Single-ended clock input ...
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... DDO I Power Supply Current DD Table 4B. Power Supply DC Characteristics, V Symbol Parameter V Positive Supply Voltage DD V Output Supply Voltage DDO I Power Supply Current DD IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR Outputs CLK nCLK Q[0:11 LOW 1 0 HIGH 0 Biased; NOTE 1 LOW 1 Biased; NOTE 1 HIGH ...
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... NOTE 1: Outputs capable of driving 50 See Parameter Measurement section, Output Load AC Test Circuit diagrams. NOTE 2: V should not be less than -0.3V. IL NOTE 3: Common mode voltage is defined as V IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR = 3.3V ± 5 DDO Test Conditions = -40°C to 85°C Test Conditions ...
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... NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: Setup and Hold times are relative to the rising edge of the input clock. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65. IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR = V = 3.3V ± 5 -40°C to 85°C ...
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... NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: Setup and Hold times are relative to the rising edge of the input clock. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65. IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR = V = 2.5V ± 5 -40°C to 85°C ...
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... NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: Setup and Hold times are relative to the rising edge of the input clock. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65. IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR = 3.3V ± 5 2.5V ± 5 ...
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... Often the noise floor of the equipment is higher than the noise floor of the IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental ...
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... Core/2.5V LVCMOS Output Load AC Test Circuit Part 1 V DDO Qx 2 Part 2 V DDO Qy 2 tsk(pp) Part-to-Part Skew IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR 1.25V±5% SCOPE V DD, V DDO Qx GND -1.25V±5% 2.5V Core/2.5V LVCMOS Output Load AC Test Circuit V DD SCOPE ...
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... LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER Parameter Measurement Information, continued 2V 0.8V Q0:Q11 t R 3.3V Output Rise/Fall Time CLK nCLK CLK V DDO 2 Q0:Q11 t PD Propagation Delay IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR 2V 0.8V Q0:Q11 t F 2.5V Output Rise/Fall Time Q0:Q11 Output Duty Cycle/Pulse Width/Period 10 1.8V 1.8V 0. DDO 2 t ...
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... LVCMOS Control Pins All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR / Single Ended Clock Input Figure 1. Single-Ended Signal Driving Differential Input ...
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... Please consult with the vendor of the driver component to and confirm the driver termination requirements. For example, in Figure PP 2A, the input termination applies for IDT open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3 ...
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... Air Flow Table for a 32 Lead LQFP JA Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards Transistor Count The transistor count for ICS83948I-147 is: 1040 Pin compatible with the MPC9448 IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR vs. Air Flow 73.6°C/W 63.9° ...
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... JEDEC Variation: ABC - HD All Dimensions in Millimeters Symbol Minimum Nominal 0.05 0.10 A2 1.35 1.40 b 0.30 0.37 c 0.09 D & E 9.00 Basic D1 & E1 7.00 Basic D2 & E2 5.60 Ref. e 0.80 Basic L 0.45 0.60 0° ccc Reference Document: JEDEC Publication 95, MS-026 IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR Maximum 1.60 0.15 1.45 0.45 0.20 0.75 7° 0.10 14 ICS83948AYI-147 REV. D NOVEMBER 1, 2012 ...
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... ICS948AI147L 83948AYI-147ILFT ICS948AI147L NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR Package Shipping Packaging 32 Lead LQFP 32 Lead LQFP “Lead-Free” 32 Lead LQFP “ ...
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... T4C 4 T5C IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR Description of Change Features Section - added Lead-Free bullet. Pin Characteristics Table - changed C added 5 min. and 12 max to R OUT Updated Single Ended Signal Driving Differential Input diagram. Added Recommendations for Unused Input and Output Pins. ...
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... IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to signif- icantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. ...