8633AF-01LF IDT, 8633AF-01LF Datasheet
8633AF-01LF
Specifications of 8633AF-01LF
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8633AF-01LF Summary of contents
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... CLK1 1 nCLK1 PLL CLK_SEL FB_IN nFB_IN SEL0 SEL1 MR 8633AF- EATURES Three differential 3.3V LVPECL outputs Selectable differential clock inputs CLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL Output frequency range: 31.25MHz to 700MHz Input frequency range: 31 ...
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... 8633AF- ...
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... D TO 4.6V NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the + 0.5V CC device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions be- yond those listed in the DC Characteristics or AC Character- istics is not implied. Exposure to absolute maximum rating 49° ...
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... 8633AF- 3.3V±5 CCA CCO ...
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... O S UTPUT KEW 80% Clock 20% Outputs UTPUT ISE ALL IME nCLK0, nCLK1 CLK0, CLK1 nQ0:nQ2 Q0: ROPAGATION ELAY 8633AF- EASUREMENT NFORMATION V CC SCOPE Qx nCLK0, nCLK1 V PP nQx CLK0, CLK1 IFFERENTIAL NPUT nQ0:nQ2 Q0: YCLE ...
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... Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ V generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio Single Ended Clock Input F IGURE 8633AF- PPLICATION ...
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... R4 125 125 Ohm Ohm LVPECL 3C. CLK/nCLK I D IGURE NPUT RIVEN BY 3.3V LVPECL D RIVER 8633AF- NPUT AND UTPUT INS O : UTPUTS LVPECL O UTPUT All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated ...
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... 4A. LVPECL O IGURE UTPUT 8633AF- transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock lay- outs may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations ...
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... CLK_SEL PLL_SEL SEL0 SEL1 RD2 RD3 RD4 RD5 Spare Footprint F 5. ICS8633-01 LVPECL Z IGURE 8633AF- termination example is shown in this schematic. Additional termination approaches are shown in the LVPECL Termi- nation Application Note. VCC R7 VCCA 10 C16 10u C11 0.01u U1 ...
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... This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer 28- ABLE HERMAL ESISTANCE FOR JA Multi-Layer PCB, JEDEC Standard Test Boards 8633AF- OWER ONSIDERATIONS = 3. 3.465V, which gives worst case results 3.465V * 150mA = 519.75mW * Pd_total + T ...
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... Pd_L is the power dissipation when the output drives low. Pd_H = [(V – 2V))/ OH_MAX CCO_MAX L [(2V - 0.9V)/ 0.9V = 19.2mW Pd_L = [(V – 2V))/ OL_MAX CCO_MAX L [(2V - 1.7V)/ 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW 8633AF- CCO Q1 6. LVPECL RIVER IRCUIT AND – 0.9V CCO_MAX – 1.7V CCO_MAX - [( ...
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... ABLE VS IR LOW ABLE FOR JA Multi-Layer PCB, JEDEC Standard Test Boards T C RANSISTOR OUNT The transistor count for ICS8633-01 is: 2969 8633AF- ELIABILITY NFORMATION 28 L SSOP EAD by Velocity (Linear Feet per Minute 49°C/W www.idt.com 12 ICS8633-01 - -3.3V LVPECL ...
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... ACKAGE UTLINE UFFIX FOR T ABLE Reference Document: JEDEC Publication 95, MO-150 8633AF- SSOP EAD ACKAGE IMENISIONS ...
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... Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. 8633AF-01 1- ...
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... 8633AF- ...
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... Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA 8633AF- ...