ICS8633AF-01LF IDT, Integrated Device Technology Inc, ICS8633AF-01LF Datasheet
ICS8633AF-01LF
Specifications of ICS8633AF-01LF
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ICS8633AF-01LF Summary of contents
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G D ENERAL ESCRIPTION The ICS8633- high performance 1-to-3 Differential-to-3.3V LVPECL Zero Delay Buffer. The ICS8633-01 has two selectable clock inputs. The CLKx, nCLKx pairs can accept most standard differential input levels. Utilizing one of the outputs as ...
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ABLE IN ESCRIPTIONS ...
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BSOLUTE AXIMUM ATINGS Supply Voltage Inputs, V -0. Outputs Continuous Current 50mA Surge Current 100mA Package Thermal Impedance, JA Storage Temperature, T -65°C to 150°C STG T 4A ...
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T 4D. LVPECL DC C ABLE HARACTERISTICS ...
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P ARAMETER CCA V CCO LVPECL V EE -1.3V ± 0.165V 3. UTPUT OAD EST IRCUIT nQx Qx nQy Qy t sk( UTPUT KEW 80% Clock 20% ...
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OWER UPPLY ILTERING ECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS8633-01 provides separate power supplies to isolate any high switching noise from the outputs to ...
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R U ECOMMENDATIONS FOR NUSED I : NPUTS CLK/nCLK I : NPUT For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection resistor ...
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T LVPECL O ERMINATION FOR UTPUTS The clock layout topology shown below is a typical termina- tion for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that gen- ...
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PPLICATION CHEMATIC XAMPLE Figure 5 shows an example of ICS8633-01 application sche- matic. The CLK/nCLK input can be driven by several types of differential input levels. In this example, the input is driven by a 3.3V LVPECL ...
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This section provides information on power dissipation and junction temperature for the ICS8633-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8633-01 is the sum of the core power plus the power ...
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Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. F IGURE T o calculate worst case power dissipation into the ...
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ABLE VS IR LOW ABLE FOR JA Multi-Layer PCB, JEDEC Standard Test Boards T C RANSISTOR OUNT The transistor count for ICS8633-01 is: 2969 8633AF- ELIABILITY NFORMATION 28 ...
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ACKAGE UTLINE UFFIX FOR T ABLE Reference Document: JEDEC Publication 95, MO-150 8633AF- SSOP EAD ACKAGE IMENISIONS ...
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T 10 ABLE RDERING NFORMATION ...
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8633AF- ...
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We’ve Got Your Timing Solution. 6024 Silver Creek Valley Road San Jose, CA 95138 © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of ...