IDT77010L155PQF IDT, Integrated Device Technology Inc, IDT77010L155PQF Datasheet

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IDT77010L155PQF

Manufacturer Part Number
IDT77010L155PQF
Description
TRANSLATION DEVICE DPI 80-PQFP
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT77010L155PQF

Applications
Data Interface
Interface
DPI, UTOPIA
Voltage - Supply
3.3V, 5V
Package / Case
80-MQFP, 80-PQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
77010L155PQF

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Bonase Electronics (HK) Co., Limited Bonase Electronics (HK) Co., Limited
Part Number:
IDT77010L155PQF
Manufacturer:
IDT
Quantity:
275
Price:
Features
Features
Features
Features
Description
Description
Description
Description
Data Path Interface (DPI). Examples of PHY devices may include the
IDT77105, and the IDT77V400 Switching Memory is an example of a
component that utilizes a DPI interface. Figure 1 illustrates a typical
application using the IDT77010.
with the DPI-4 interface capable of full duplex operation at 160 Mbps.
ters, with the Control Cells being generated from a remote controlling
agent. The Control Cells are used to configure, control and retrieve
status of the PHY device.
Block Diagram
Block Diagram
Block Diagram
Block Diagram
 2002 Integrated Device Technology, Inc.
The 77010 interfaces a UTOPIA PHY device to a device that uses a
The UTOPIA level 1 bus interface runs at speeds up to 155 Mbps,
In-stream programming is used to read and write to the PHY regis-
!
!
!
!
!
!
Single chip ATM Layer UTOPIA Level 1 to 4-bit DPI interface.
Supports ATM Forum UTOPIA Level 1 interface.
Supports ATM device interface in Cell mode.
Capable of full-duplex operation up-to 160 Mbps.
Utility bus interface to access PHY registers.
In-stream control to access PHY registers.
STS-3
OC-3
or
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
Data Path Interface (DPI) to
Utopia Level 1
Translation Device
OC-3
PHY
"
"
"
Figure 1 Typical IDT77010 Application
UTOPIA L1
Utility bus
UTOPIA L1
Receive
Transmit
1 of 21
UTOPIA L1
IDT77010
to DPI I/F
Theory of Operation
Theory of Operation
Theory of Operation
Theory of Operation
at a time. The DPI-4 clock rate is twice the frequency of receive UTOPIA
clock.
cell at a time. Transmit flow control is used to match the transmit cell rate
to the PHY's transmit cell rate.
The control cells are filtered and will not be transferred to the UTOPIA
transmit bus.
the Utility Bus Interface to execute the commands. For a Utility bus write
command cell, the Utility bus does a one byte write to the specified
Utility bus address. For a Utility bus read command cell, the Utility bus
reads one byte from the specified Utility bus address and loads this byte
to the Cell Generator logic. The Cell Generator makes a request to the
receive cell arbiter to process the cell, and generates a status cell if no
UTOPIA receive cell is detected.
Receive DPI-4 I/F logic.
UTOPIA bus or a status ATM cell locally generated. Internally generated
ATM cells are output to the Receive DPI-4 Interface only when there are
no UTOPIA Receive cell. Figure 2 below shows the device data flow.
"
"
"
UTOPIA receive cells are transferred to the DPI-4 interface one cell
DPI-4 transmit cells are transferred to the UTOPIA transmit bus one
Control cells are inserted and decoded by the control cell decoder.
The control cell decoder block identifies the control cells and signals
A status cell is a complete ATM cell generated and loaded to the
A receive cell on the DPI-4 bus is either an ATM cell from the receive
DPI Receive
DPI Transmit
4
4
IDT77V400
4308 drw 01
Switching
Memory
.
June 24, 2002
IDT77010
DSC 4308/4

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IDT77010L155PQF Summary of contents

Page 1

Features Features Features Features ! Single chip ATM Layer UTOPIA Level 1 to 4-bit DPI interface. ! Supports ATM Forum UTOPIA Level 1 interface. ! Supports ATM device interface in Cell mode. ! Capable of full-duplex operation up-to 160 Mbps. ...

Page 2

IDT77010 Block Diagram Block Diagram Block Diagram Block Diagram 8 UTOPIA Interface 8 8 Pin Configuration Pin Configuration Pin Configuration Pin Configuration 1,2 1,2 1,2 1,2 INDEX DATA7 X T DATA6 X T DATA5 X T DATA4 ...

Page 3

IDT77010 Pin Definitions Pin Definitions Pin Definitions Pin Definitions Pin Input/ Signal Name Number Output SysClk 29 I RST 23 I LCRST 24 I CONT_A 19 O CONT_B 22 O RxLED 42 O TxLED 79 O READ 73 O WRITE ...

Page 4

IDT77010 Pin Input/ Signal Name Number Output RxData7 55 I TENB 18 O TCLK 16 O TCLAV 17 I TSOC 2 O TxData0 13 O TxData1 12 O TxData2 11 O TxData3 10 O TxData4 9 O TxData5 6 O ...

Page 5

IDT77010 Absolute Maximum Ratings Absolute Maximum Ratings Absolute Maximum Ratings Absolute Maximum Ratings Symbol V 5V Digital Supply Voltage CC V 3.3V Digital Supply Voltage DD V Digital Input Voltage IN I Output Current OUT T Storage Temperature STG Recommended ...

Page 6

IDT77010 Device Interface Device Interface Device Interface Device Interface This 77010 uses a UTOPIA level 1 interface to receive and transmit ATM cells to and from the PHY device. It mirrors the ATM layer as shown in Figure 3 below. ...

Page 7

IDT77010 UTOPIA Receive Interface Operation UTOPIA Receive Interface Operation UTOPIA Receive Interface Operation UTOPIA Receive Interface Operation UTOPIA cell level handshake is used to receive an ATM cell from a UTOPIA PHY device. The UTOPIA Receive Clock (RCLK ...

Page 8

IDT77010 Input Control Cell Formatting Input Control Cell Formatting Input Control Cell Formatting Input Control Cell Formatting Control cells are generated by a remote computer and are used to configure and monitor the PHY registers. All cells having the header ...

Page 9

IDT77010 Cell Byte Bit Function Number Number . 7-0 reserved . 7-0 reserved 52 7-0 reserved 1. This value can be programmed by instream control cells. DPI Bus Data Sequence DPI Bus Data Sequence DPI Bus Data Sequence DPI Bus ...

Page 10

IDT77010 Receive DPI Bus Interface Receive DPI Bus Interface Receive DPI Bus Interface Receive DPI Bus Interface The Receive DPI Clock (DRxCLK continuous clock generated from SYSCLK and is twice the frequency of RCLK. The Receive Start of ...

Page 11

IDT77010 Utility Bus Read Operation Utility Bus Read Operation Utility Bus Read Operation Utility Bus Read Operation When the 77010 decodes the command cells for a Utility bus read operation, it drives the PHY chip select (PHYCS), Address Latch Enable ...

Page 12

IDT77010 Command Cells Command Cells Command Cells Command Cells Reset PHY Chip Command Reset PHY Chip Command Reset PHY Chip Command Reset PHY Chip Command Resets the PHY device and the Utility bus. PHYRST will assert low for 16 SYSCLK ...

Page 13

IDT77010 Status Read Command Status Read Command Status Read Command Status Read Command This command reads the 77010 Revision number and the Interrupt pin state, and causes an internally generated cell. See internally generated cell format section. Command Fields Field ...

Page 14

IDT77010 Internally Generated Reply Cell Table - Data A Internally Generated Reply Cell Table - Data A Internally Generated Reply Cell Table - Data A Internally Generated Reply Cell Table - Data A Internally Generated Cell Type Utility Bus Read ...

Page 15

IDT77010 Symbol t SCLK Cycle Time CYC t SCLK High Time CH t SCLK Low Time CL t UTOPIA TCLK/RCLK Cycle Time UCYC t UTOPIA TCLK/RCLK High Time UCH t UTOPIA TCLK/RCLK Low Time UCL t TxDATA, TxPRTY, TENB, TSOC ...

Page 16

IDT77010 Symbol t System Clock to Utopia Transmit Clock Propagation Delay PTCLK t System Clock to DPI Receive Clock Propagation Delay PDRxCLK t System Clock to DPI Transmit Clock Propagation Delay PDTxCLK t System Clock to RxLED Propagation Delay PRLED ...

Page 17

IDT77010 System Clock Timing Waveform System Clock Timing Waveform System Clock Timing Waveform System Clock Timing Waveform SYSCLK UTOPIA Transmit Timing Waveform UTOPIA Transmit Timing Waveform UTOPIA Transmit Timing Waveform UTOPIA Transmit Timing Waveform TxDATA(0-7), TENB, TSOC TCLAV UTOPIA Receive ...

Page 18

IDT77010 System Clock to UTOPIA Receive Clock Propagation Delay System Clock to UTOPIA Receive Clock Propagation Delay System Clock to UTOPIA Receive Clock Propagation Delay System Clock to UTOPIA Receive Clock Propagation Delay SYSCLK RCLK System Clock to UTOPIA Transmit ...

Page 19

IDT77010 System Clock to Count_A Propagation Delay System Clock to Count_A Propagation Delay System Clock to Count_A Propagation Delay System Clock to Count_A Propagation Delay SYSCLK CONT_A System Clock to Count_B Propagation Delay System Clock to Count_B Propagation Delay System ...

Page 20

IDT77010 Package Information Package Information Package Information Package Information Plastic QFP 80pin Body size 1.4mm (QFP14 Symbol Min E 11 0.13 C 0.1 q ...

Page 21

IDT77010 Ordering Information Ordering Information Ordering Information Ordering Information IDT XXXXX A 999 Device Power Speed Type Data Sheet Document History Data Sheet Document History Data Sheet Document History Data Sheet Document History 4/02/99 Changed format 5/18/99 Changed tDTH from ...

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