IDT77010L155PQF IDT, Integrated Device Technology Inc, IDT77010L155PQF Datasheet - Page 8

• Manufacturer Part Number: IDT77010L155PQF
• Description: TRANSLATION DEVICE DPI 80-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77010L155PQF

• Applications: Data Interface
• Interface: DPI, UTOPIA
• Voltage - Supply: 3.3V, 5V
• Package / Case: 80-MQFP, 80-PQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 77010L155PQF

Input Control Cell Formatting
Input Control Cell Formatting
Input Control Cell Formatting
Input Control Cell Formatting
configure and monitor the PHY registers. All cells having the header VPI
= 0x00 hex and VCI = 0x1F hex (VCI bits 11-4) are decoded and
executed as control cells by the 77010.
Control Cell Filter Operation
Control Cell Filter Operation
Control Cell Filter Operation
Control Cell Filter Operation
they are control cells.Cells containing the header VPI = 00 Hex and VCI
= 1F Hex (VCI bits 11-4) are filtered as control cells and not forwarded to
the TxDATA[7:0] bus. The filter ignores the GFC, PTI and CLP bits. The
default control cell identifier value is 00x1F. It can be programmed to a
user defined value via the Change Control Cell Address Command (see
page 16).
Control Cell Frequency
Control Cell Frequency
Control Cell Frequency
Control Cell Frequency
nations, and are terminated (filtered) by the 77010.
internally generated control cells. The control cell is ignored if a previous
control cell is being executed at that time. A gap in the UTOPIA cell
stream must occur before the new control cell is processed, because the
UTOPIA receive cells have higher priority.
control cell will not be processed and could be dropped, even though the
77010 can filter both of them. Worst case condition is when the receive
Control ATM Cell Format
Control ATM Cell Format
Control ATM Cell Format
Control ATM Cell Format
0
0
1
1
2
3
3
3
4
5
6
7
8
IDT77010
Control cells are generated by a remote computer and are used to
All cells transferred over the DTxDATA[3:0] bus are tested to see if
The control cells arrive multiplexed with data cells in random combi-
The RxDATA[3:0] bus multiplexes the receive UTOPIA cells and any
Control cells may be input back-to-back. However, the second
Cell Byte
Number
7-4
3-0
7-4
3-0
7-0
7-4
3-1
0
7-0
7-0
7-0
7-0
7-0
Number
Bit
GFC
VPI 7-4
VPI 3-0
VCI 15-12
VCI 11-4
VCI 3-0
PTI
CLP
HEC
Command
Data A
Data B
reserved
Function
Name
0xX
0x0
0x0
0x0
0xYY
0x0
000'b
0'b
0x00
00-FF Hex
0x0 - 0xFF
0x0 - 0xFF
0x00
Contents
Bit
8 of 21
Don't care.
Must be set to 0x0.
Must be set to 0x0.
Must be set to 0x0.
Special VCI value for control and status cells. Default is 0x1F.
Don't care.
Don't care.
Don't care.
Don't care.
Command cell byte.
Parameter for control cell.
Parameter for control cell.
Always set to 0x00.
control cells be at least 50 cells apart.
DPI Interface Operation
DPI Interface Operation
DPI Interface Operation
DPI Interface Operation
transfer ATM cells between two devices. The 77010 contains a DPI-4
bus interface, which contains a four bit wide data bus. Therefore, 107
clock cycles are required to transfer a 53 byte ATM cell.
each requiring six signals. The signals are a clock, a start of cell marker
and a four bit data bus. All signals are sampled on the rising edge of
their respective clock.
Transmit DPI Bus Interface
Transmit DPI Bus Interface
Transmit DPI Bus Interface
Transmit DPI Bus Interface
twice the frequency of TCLK. This clock is not continuous and is used to
control data flow to the PHY device. DTxCLK is initially low and not
driven until the 77010 detects a high TCLAV from the PHY device. On
the rising edge of DTxCLK the 77010 samples Transmit Start of Cell
(DTxFRM), which is generated by the transmitting device for one
DTxCLK cycle. When DTxFRM is asserted high the 77010 will sample
valid data (DTxDATA[3:0]) on the next rising edge of DTxCLK. Cell
transfer will continue without interruption once it has started.
DTxCLK goes low until another high TCLAV is detected.
DTxCLK.
UTOPIA bus is at full rate. In this case it is recommended that the
Data Path Interface (DPI) is a synchronous bus interface designed to
The 77010 has separate DPI-4 transmit and receive interfaces, with
The Transmit DPI Clock (DTxCLK) is generated from SYSCLK and is
When TCLAV is de-asserted low the current cell is transferred and
DTxFRM and DTxDATA[3:0] are sampled on the rising edge of
Description
1
June 24, 2002